Home
last modified time | relevance | path

Searched refs:mmCP_RB_WPTR_POLL_CNTL (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDmxgpu_vi.c81 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
212 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
HDgfx_v9_0.c2049 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); in gfx_v9_0_init_gfx_power_gating()
2052 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); in gfx_v9_0_init_gfx_power_gating()
3646 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_3d_clock_gating()
3650 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_3d_clock_gating()
3696 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_coarse_grain_clock_gating()
3700 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
HDgfx_v8_0.c299 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
462 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
563 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
669 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h524 #define mmCP_RB_WPTR_POLL_CNTL 0x21C2 macro
HDgfx_7_0_d.h513 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
HDgfx_7_2_d.h526 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
HDgfx_8_0_d.h579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
HDgfx_8_1_d.h579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h212 #define mmCP_RB_WPTR_POLL_CNTL … macro
HDgc_9_2_1_offset.h206 #define mmCP_RB_WPTR_POLL_CNTL … macro
HDgc_9_1_offset.h212 #define mmCP_RB_WPTR_POLL_CNTL … macro