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Searched refs:mmCP_RB_WPTR_POLL_ADDR_LO (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h523 #define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 macro
HDgfx_7_0_d.h218 #define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 macro
HDgfx_7_2_d.h218 #define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 macro
HDgfx_8_0_d.h242 #define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 macro
HDgfx_8_1_d.h243 #define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h2342 #define mmCP_RB_WPTR_POLL_ADDR_LO … macro
HDgc_9_2_1_offset.h2594 #define mmCP_RB_WPTR_POLL_ADDR_LO … macro
HDgc_9_1_offset.h2656 #define mmCP_RB_WPTR_POLL_ADDR_LO … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v9_0.c2486 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); in gfx_v9_0_cp_gfx_resume()
HDgfx_v8_0.c4507 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); in gfx_v8_0_cp_gfx_resume()