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Searched refs:mmCP_PWR_CNTL (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h492 #define mmCP_PWR_CNTL 0x3078 macro
HDgfx_7_0_d.h254 #define mmCP_PWR_CNTL 0x3078 macro
HDgfx_7_2_d.h256 #define mmCP_PWR_CNTL 0x3078 macro
HDgfx_8_0_d.h288 #define mmCP_PWR_CNTL 0x3078 macro
HDgfx_8_1_d.h288 #define mmCP_PWR_CNTL 0x3078 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h2438 #define mmCP_PWR_CNTL … macro
HDgc_9_2_1_offset.h2690 #define mmCP_PWR_CNTL … macro
HDgc_9_1_offset.h2752 #define mmCP_PWR_CNTL … macro