Home
last modified time | relevance | path

Searched refs:mmCP_MEC_ME2_UCODE_ADDR (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h252 #define mmCP_MEC_ME2_UCODE_ADDR 0x305e macro
HDgfx_7_2_d.h254 #define mmCP_MEC_ME2_UCODE_ADDR 0x305e macro
HDgfx_8_0_d.h283 #define mmCP_MEC_ME2_UCODE_ADDR 0xf81c macro
HDgfx_8_1_d.h284 #define mmCP_MEC_ME2_UCODE_ADDR 0xf81c macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v8_0.c4580 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); in gfx_v8_0_cp_compute_load_microcode()
4583 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version); in gfx_v8_0_cp_compute_load_microcode()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h6689 #define mmCP_MEC_ME2_UCODE_ADDR macro
HDgc_9_2_1_offset.h6998 #define mmCP_MEC_ME2_UCODE_ADDR macro
HDgc_9_1_offset.h6970 #define mmCP_MEC_ME2_UCODE_ADDR macro