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Searched refs:mmCP_MEC_ME1_UCODE_DATA (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDpsp_v10_0.c355 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); in psp_v10_0_sram_map()
HDpsp_v3_1.c488 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); in psp_v3_1_sram_map()
HDgfx_v9_0.c2570 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, in gfx_v9_0_cp_compute_load_microcode()
HDgfx_v8_0.c4565 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i)); in gfx_v8_0_cp_compute_load_microcode()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h251 #define mmCP_MEC_ME1_UCODE_DATA 0x305d macro
HDgfx_7_2_d.h253 #define mmCP_MEC_ME1_UCODE_DATA 0x305d macro
HDgfx_8_0_d.h282 #define mmCP_MEC_ME1_UCODE_DATA 0xf81b macro
HDgfx_8_1_d.h283 #define mmCP_MEC_ME1_UCODE_DATA 0xf81b macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h6685 #define mmCP_MEC_ME1_UCODE_DATA … macro
HDgc_9_2_1_offset.h6994 #define mmCP_MEC_ME1_UCODE_DATA … macro
HDgc_9_1_offset.h6966 #define mmCP_MEC_ME1_UCODE_DATA … macro