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Searched refs:mmCP_ME0_PIPE1_VMID (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_2_d.h241 #define mmCP_ME0_PIPE1_VMID 0x3053 macro
HDgfx_8_0_d.h265 #define mmCP_ME0_PIPE1_VMID 0x3053 macro
HDgfx_8_1_d.h266 #define mmCP_ME0_PIPE1_VMID 0x3053 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h2376 #define mmCP_ME0_PIPE1_VMID … macro
HDgc_9_2_1_offset.h2628 #define mmCP_ME0_PIPE1_VMID … macro
HDgc_9_1_offset.h2690 #define mmCP_ME0_PIPE1_VMID … macro