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Searched refs:mmCP_HQD_IQ_TIMER (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDamdgpu_amdkfd_gfx_v8.c604 temp = RREG32(mmCP_HQD_IQ_TIMER); in kgd_hqd_destroy()
HDgfx_v9_0.c2956 WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0); in gfx_v9_0_kiq_fini_register()
HDgfx_v8_0.c4823 tmp = RREG32(mmCP_HQD_IQ_TIMER); in gfx_v8_0_mqd_init()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h589 #define mmCP_HQD_IQ_TIMER 0x325b macro
HDgfx_7_2_d.h602 #define mmCP_HQD_IQ_TIMER 0x325b macro
HDgfx_8_0_d.h652 #define mmCP_HQD_IQ_TIMER 0x325b macro
HDgfx_8_1_d.h652 #define mmCP_HQD_IQ_TIMER 0x325b macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h2799 #define mmCP_HQD_IQ_TIMER … macro
HDgc_9_2_1_offset.h3040 #define mmCP_HQD_IQ_TIMER … macro
HDgc_9_1_offset.h3084 #define mmCP_HQD_IQ_TIMER … macro