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Searched refs:mmCP_HQD_IQ_RPTR (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h590 #define mmCP_HQD_IQ_RPTR 0x325c macro
HDgfx_7_2_d.h603 #define mmCP_HQD_IQ_RPTR 0x325c macro
HDgfx_8_0_d.h653 #define mmCP_HQD_IQ_RPTR 0x325c macro
HDgfx_8_1_d.h653 #define mmCP_HQD_IQ_RPTR 0x325c macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h2801 #define mmCP_HQD_IQ_RPTR … macro
HDgc_9_2_1_offset.h3042 #define mmCP_HQD_IQ_RPTR … macro
HDgc_9_1_offset.h3086 #define mmCP_HQD_IQ_RPTR … macro