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Searched refs:mmCP_HQD_CTX_SAVE_CONTROL (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_8_0_d.h678 #define mmCP_HQD_CTX_SAVE_CONTROL 0x3272 macro
HDgfx_8_1_d.h678 #define mmCP_HQD_CTX_SAVE_CONTROL 0x3272 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h2851 #define mmCP_HQD_CTX_SAVE_CONTROL … macro
HDgc_9_2_1_offset.h3092 #define mmCP_HQD_CTX_SAVE_CONTROL … macro
HDgc_9_1_offset.h3136 #define mmCP_HQD_CTX_SAVE_CONTROL … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v8_0.c4827 tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL); in gfx_v8_0_mqd_init()