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Searched refs:mmCP_CPC_STALLED_STAT1 (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDsoc15.c291 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
HDvi.c491 {mmCP_CPC_STALLED_STAT1},
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h313 #define mmCP_CPC_STALLED_STAT1 0x2086 macro
HDgfx_7_2_d.h316 #define mmCP_CPC_STALLED_STAT1 0x2086 macro
HDgfx_8_0_d.h352 #define mmCP_CPC_STALLED_STAT1 0x2086 macro
HDgfx_8_1_d.h352 #define mmCP_CPC_STALLED_STAT1 0x2086 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h120 #define mmCP_CPC_STALLED_STAT1 … macro
HDgc_9_2_1_offset.h122 #define mmCP_CPC_STALLED_STAT1 … macro
HDgc_9_1_offset.h120 #define mmCP_CPC_STALLED_STAT1 … macro