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Searched refs:mmCPC_INT_STATUS (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h273 #define mmCPC_INT_STATUS 0x30b5 macro
HDgfx_7_2_d.h275 #define mmCPC_INT_STATUS 0x30b5 macro
HDgfx_8_0_d.h306 #define mmCPC_INT_STATUS 0x30b5 macro
HDgfx_8_1_d.h306 #define mmCPC_INT_STATUS 0x30b5 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h2551 #define mmCPC_INT_STATUS … macro
HDgc_9_2_1_offset.h2794 #define mmCPC_INT_STATUS … macro
HDgc_9_1_offset.h2860 #define mmCPC_INT_STATUS … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v9_0.c4170 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); in gfx_v9_0_ring_emit_fence_kiq()
HDgfx_v8_0.c6636 amdgpu_ring_write(ring, mmCPC_INT_STATUS); in gfx_v8_0_ring_emit_fence_kiq()