Home
last modified time | relevance | path

Searched refs:mmCGTS_CU9_SP1_CTRL_REG (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h1533 #define mmCGTS_CU9_SP1_CTRL_REG 0xf038 macro
HDgfx_7_2_d.h1554 #define mmCGTS_CU9_SP1_CTRL_REG 0xf038 macro
HDgfx_8_0_d.h1747 #define mmCGTS_CU9_SP1_CTRL_REG 0xf038 macro
HDgfx_8_1_d.h1715 #define mmCGTS_CU9_SP1_CTRL_REG 0xf038 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h6347 #define mmCGTS_CU9_SP1_CTRL_REG … macro
HDgc_9_2_1_offset.h6638 #define mmCGTS_CU9_SP1_CTRL_REG … macro
HDgc_9_1_offset.h6626 #define mmCGTS_CU9_SP1_CTRL_REG … macro