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Searched refs:mmCGTS_CU15_LDS_SQ_CTRL_REG (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h1561 #define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 macro
HDgfx_7_2_d.h1582 #define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 macro
HDgfx_8_0_d.h1775 #define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 macro
HDgfx_8_1_d.h1743 #define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h6403 #define mmCGTS_CU15_LDS_SQ_CTRL_REG … macro
HDgc_9_2_1_offset.h6694 #define mmCGTS_CU15_LDS_SQ_CTRL_REG … macro
HDgc_9_1_offset.h6682 #define mmCGTS_CU15_LDS_SQ_CTRL_REG … macro