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/dragonfly/sys/dev/raid/mlx/
HDmlx.c64 …tic int mlx_v3_tryqueue(struct mlx_softc *sc, struct mlx_command *mc);
69 …tic int mlx_v4_tryqueue(struct mlx_softc *sc, struct mlx_command *mc);
74 …tic int mlx_v5_tryqueue(struct mlx_softc *sc, struct mlx_command *mc);
83 static void mlx_periodic_enquiry(struct mlx_command *mc);
85 static void mlx_periodic_eventlog_respond(struct mlx_command *mc);
86 static void mlx_periodic_rebuild(struct mlx_command *mc);
92 static void mlx_pause_done(struct mlx_command *mc);
98 void (*complete)(struct mlx_command *mc));
102 static int mlx_wait_command(struct mlx_command *mc);
103 static int mlx_poll_command(struct mlx_command *mc);
[all …]
HDmlxreg.h503 mlx_make_type1(struct mlx_command *mc, in mlx_make_type1() argument
511 mc->mc_mailbox[0x0] = code; in mlx_make_type1()
512 mc->mc_mailbox[0x2] = f1 & 0xff; in mlx_make_type1()
513 mc->mc_mailbox[0x3] = (((f2 >> 24) & 0x3) << 6) | ((f1 >> 8) & 0x3f); in mlx_make_type1()
514 mc->mc_mailbox[0x4] = f2 & 0xff; in mlx_make_type1()
515 mc->mc_mailbox[0x5] = (f2 >> 8) & 0xff; in mlx_make_type1()
516 mc->mc_mailbox[0x6] = (f2 >> 16) & 0xff; in mlx_make_type1()
517 mc->mc_mailbox[0x7] = f3; in mlx_make_type1()
518 mc->mc_mailbox[0x8] = f4 & 0xff; in mlx_make_type1()
519 mc->mc_mailbox[0x9] = (f4 >> 8) & 0xff; in mlx_make_type1()
[all …]
/dragonfly/sys/dev/raid/mly/
HDmly.c75 static void mly_complete_rescan(struct mly_command *mc);
83 static void mly_complete_event(struct mly_command *mc);
87 static int mly_immediate_command(struct mly_command *mc);
88 static int mly_start(struct mly_command *mc);
93 static void mly_release_command(struct mly_command *mc);
97 static void mly_map_command(struct mly_command *mc);
98 static void mly_unmap_command(struct mly_command *mc);
107 static void mly_cam_complete(struct mly_command *mc);
116 static void mly_print_command(struct mly_command *mc);
117 static void mly_print_packet(struct mly_command *mc);
[all …]
HDmlyvar.h142 void (* mc_complete)(struct mly_command *mc); /* completion handler */
317 mly_enqueue_ ## name (struct mly_command *mc) \
320 TAILQ_INSERT_TAIL(&mc->mc_sc->mly_ ## name, mc, mc_link); \
321 MLYQ_ADD(mc->mc_sc, index); \
325 mly_requeue_ ## name (struct mly_command *mc) \
328 TAILQ_INSERT_HEAD(&mc->mc_sc->mly_ ## name, mc, mc_link); \
329 MLYQ_ADD(mc->mc_sc, index); \
335 struct mly_command *mc; \
338 if ((mc = TAILQ_FIRST(&sc->mly_ ## name)) != NULL) { \
339 TAILQ_REMOVE(&sc->mly_ ## name, mc, mc_link); \
[all …]
/dragonfly/sys/dev/drm/radeon/
HDr520.c97 rdev->mc.vram_width = 128; in r520_vram_get_type()
98 rdev->mc.vram_is_ddr = true; in r520_vram_get_type()
102 rdev->mc.vram_width = 32; in r520_vram_get_type()
105 rdev->mc.vram_width = 64; in r520_vram_get_type()
108 rdev->mc.vram_width = 128; in r520_vram_get_type()
111 rdev->mc.vram_width = 256; in r520_vram_get_type()
114 rdev->mc.vram_width = 128; in r520_vram_get_type()
118 rdev->mc.vram_width *= 2; in r520_vram_get_type()
126 radeon_vram_location(rdev, &rdev->mc, 0); in r520_mc_init()
127 rdev->mc.gtt_base_align = 0; in r520_mc_init()
[all …]
HDradeon_device.c587 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) in radeon_vram_location() argument
591 mc->vram_start = base; in radeon_vram_location()
592 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { in radeon_vram_location()
594 mc->real_vram_size = mc->aper_size; in radeon_vram_location()
595 mc->mc_vram_size = mc->aper_size; in radeon_vram_location()
597 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in radeon_vram_location()
598 …if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { in radeon_vram_location()
600 mc->real_vram_size = mc->aper_size; in radeon_vram_location()
601 mc->mc_vram_size = mc->aper_size; in radeon_vram_location()
603 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in radeon_vram_location()
[all …]
HDrv770.c922 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in rv770_pcie_gart_enable()
923 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in rv770_pcie_gart_enable()
934 (unsigned)(rdev->mc.gtt_size >> 20), in rv770_pcie_gart_enable()
1028 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in rv770_mc_program()
1031 rdev->mc.vram_start >> 12); in rv770_mc_program()
1033 rdev->mc.gtt_end >> 12); in rv770_mc_program()
1037 rdev->mc.gtt_start >> 12); in rv770_mc_program()
1039 rdev->mc.vram_end >> 12); in rv770_mc_program()
1043 rdev->mc.vram_start >> 12); in rv770_mc_program()
1045 rdev->mc.vram_end >> 12); in rv770_mc_program()
[all …]
HDrs400.c39 switch (rdev->mc.gtt_size/(1024*1024)) { in rs400_gart_adjust_size()
50 (unsigned)(rdev->mc.gtt_size >> 20)); in rs400_gart_adjust_size()
53 rdev->mc.gtt_size = 32 * 1024 * 1024; in rs400_gart_adjust_size()
83 switch(rdev->mc.gtt_size / (1024 * 1024)) { in rs400_gart_init()
114 switch(rdev->mc.gtt_size / (1024 * 1024)) { in rs400_gart_enable()
147 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); in rs400_gart_enable()
148 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); in rs400_gart_enable()
186 (unsigned)(rdev->mc.gtt_size >> 20), in rs400_gart_enable()
266 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); in rs400_mc_init()
268 rdev->mc.vram_is_ddr = true; in rs400_mc_init()
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HDradeon_agp.c244 rdev->mc.agp_base = rdev->ddev->agp->agp_info.ai_aperture_base; in radeon_agp_init()
245 rdev->mc.gtt_size = rdev->ddev->agp->agp_info.ai_aperture_size << 20; in radeon_agp_init()
246 rdev->mc.gtt_start = rdev->mc.agp_base; in radeon_agp_init()
247 rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_size - 1; in radeon_agp_init()
249 rdev->mc.gtt_size >> 20, rdev->mc.gtt_start, rdev->mc.gtt_end); in radeon_agp_init()
HDradeon_object.c106 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { in radeon_ttm_placement_from_domain()
108 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; in radeon_ttm_placement_from_domain()
171 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; in radeon_ttm_placement_from_domain()
344 domain_start = bo->rdev->mc.vram_start; in radeon_bo_pin_restricted()
346 domain_start = bo->rdev->mc.gtt_start; in radeon_bo_pin_restricted()
363 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) in radeon_bo_pin_restricted()
365 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; in radeon_bo_pin_restricted()
424 if (rdev->mc.igp_sideport_enabled == false) in radeon_bo_evict_vram()
454 arch_io_reserve_memtype_wc(rdev->mc.aper_base, in radeon_bo_init()
455 rdev->mc.aper_size); in radeon_bo_init()
[all …]
HDrs690.c155 rdev->mc.vram_is_ddr = true; in rs690_mc_init()
156 rdev->mc.vram_width = 128; in rs690_mc_init()
157 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in rs690_mc_init()
158 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in rs690_mc_init()
159 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in rs690_mc_init()
160 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in rs690_mc_init()
161 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rs690_mc_init()
164 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in rs690_mc_init()
169 if (rdev->mc.igp_sideport_enabled && in rs690_mc_init()
170 (rdev->mc.real_vram_size == (384 * 1024 * 1024))) { in rs690_mc_init()
[all …]
HDrs600.c593 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); in rs600_gart_enable()
594 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); in rs600_gart_enable()
598 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); in rs600_gart_enable()
599 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); in rs600_gart_enable()
608 (unsigned)(rdev->mc.gtt_size >> 20), in rs600_gart_enable()
871 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in rs600_mc_init()
872 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in rs600_mc_init()
873 rdev->mc.vram_is_ddr = true; in rs600_mc_init()
874 rdev->mc.vram_width = 128; in rs600_mc_init()
875 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in rs600_mc_init()
[all …]
HDradeon_ttm.c143 man->gpu_offset = rdev->mc.gtt_start; in radeon_init_mem_type()
165 man->gpu_offset = rdev->mc.vram_start; in radeon_init_mem_type()
201 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && in radeon_evict_flags()
202 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { in radeon_evict_flags()
203 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; in radeon_evict_flags()
274 old_start += rdev->mc.vram_start; in radeon_move_blit()
277 old_start += rdev->mc.gtt_start; in radeon_move_blit()
285 new_start += rdev->mc.vram_start; in radeon_move_blit()
288 new_start += rdev->mc.gtt_start; in radeon_move_blit()
482 mem->bus.base = rdev->mc.agp_base; in radeon_ttm_io_mem_reserve()
[all …]
HDradeon_fb.c284 unsigned long tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; in radeonfb_create()
286 info->paddr = rdev->mc.aper_base + tmp; in radeonfb_create()
294 tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; in radeonfb_create()
295 info->fix.smem_start = rdev->mc.aper_base + tmp; in radeonfb_create()
304 info->apertures->ranges[0].size = rdev->mc.aper_size; in radeonfb_create()
315 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base); in radeonfb_create()
374 if (rdev->mc.real_vram_size <= (8*1024*1024)) in radeon_fbdev_init()
377 rdev->mc.real_vram_size <= (32*1024*1024)) in radeon_fbdev_init()
/dragonfly/test/stress/stress2/misc/
HDldt.sh303 mcontext_t *mc;
306 mc = &uc->uc_mcontext;
308 run, mc->mc_err, mc->mc_ds, mc->mc_ss, mc->mc_es, mc->mc_fs,
309 mc->mc_gs);
312 mc->mc_ds = 0x1111;
315 mc->mc_es = 0x1111;
318 mc->mc_fs = 0x1111;
321 mc->mc_gs = 0x1111;
324 mc->mc_ss = 0x1111;
/dragonfly/libexec/bootpd/
HDChanges10 03/27/96 gwr@mc.com (Gordon W. Ross)
15 03/25/95 gwr@mc.com (Gordon W. Ross)
46 08/24/94 gwr@mc.com (Gordon W. Ross)
52 08/24/94 gwr@mc.com (Gordon W. Ross)
57 08/20/94 gwr@mc.com (Gordon W. Ross)
75 05/27/94 gwr@mc.com (Gordon W. Ross)
86 04/30/94 gwr@mc.com (Gordon W. Ross)
94 04/27/94 gwr@mc.com
102 04/16/94 gwr@mc.com (Gordon W. Ross)
129 03/07/94 gwr@mc.com
[all …]
/dragonfly/games/sail/
HDpl_3.c60 crew[0] = mc->crew1; in acceptcombat()
61 crew[1] = mc->crew2; in acceptcombat()
62 crew[2] = mc->crew3; in acceptcombat()
80 guns = mc->gunR; in acceptcombat()
81 car = mc->carR; in acceptcombat()
85 guns = mc->gunL; in acceptcombat()
86 car = mc->carL; in acceptcombat()
151 hit += QUAL[index][mc->qual-1]; in acceptcombat()
172 if (((temp = mc->class) >= 5 || temp == 1) && windspeed == 5) in acceptcombat()
HDpl_7.c96 struct shipspecs *mc; /* ms->specs */ variable
629 wprintw(stat_w, "Hull %2d\n", mc->hull); in draw_stat()
631 mc->crew1, mc->crew2, mc->crew3); in draw_stat()
632 wprintw(stat_w, "Guns %2d %2d\n", mc->gunL, mc->gunR); in draw_stat()
633 wprintw(stat_w, "Carr %2d %2d\n", mc->carL, mc->carR); in draw_stat()
634 wprintw(stat_w, "Rigg %d %d %d ", mc->rig1, mc->rig2, mc->rig3); in draw_stat()
635 if (mc->rig4 < 0) in draw_stat()
638 wprintw(stat_w, "%d", mc->rig4); in draw_stat()
757 mc->class, in draw_board()
758 classname[mc->class], in draw_board()
[all …]
/dragonfly/etc/sendmail/
HDMakefile.4install69 SENDMAIL_MC:= ${SENDMAIL_MC}.mc
72 cp dragonfly.mc ${SENDMAIL_MC}
77 SENDMAIL_SUBMIT_MC:= ${SENDMAIL_SUBMIT_MC}.submit.mc
80 cp dragonfly.submit.mc ${SENDMAIL_SUBMIT_MC}
159 .SUFFIXES: .cf .mc
161 .mc.cf: ${M4FILES}
163 ${SENDMAIL_CF_DIR}/m4/cf.m4 ${@:R}.mc > ${.TARGET}
/dragonfly/sys/bus/u4b/audio/
HDuaudio.c3035 uaudio_mixer_add_ctl_sub(struct uaudio_softc *sc, struct uaudio_mixer_node *mc) in uaudio_mixer_add_ctl_sub() argument
3042 memcpy(p_mc_new, mc, sizeof(*p_mc_new)); in uaudio_mixer_add_ctl_sub()
3070 uaudio_mixer_add_ctl(struct uaudio_softc *sc, struct uaudio_mixer_node *mc) in uaudio_mixer_add_ctl() argument
3074 if (mc->class < UAC_NCLASSES) { in uaudio_mixer_add_ctl()
3076 uac_names[mc->class], mc->ctl); in uaudio_mixer_add_ctl()
3078 DPRINTF("adding %d\n", mc->ctl); in uaudio_mixer_add_ctl()
3081 if (mc->type == MIX_ON_OFF) { in uaudio_mixer_add_ctl()
3082 mc->minval = 0; in uaudio_mixer_add_ctl()
3083 mc->maxval = 1; in uaudio_mixer_add_ctl()
3084 } else if (mc->type == MIX_SELECTOR) { in uaudio_mixer_add_ctl()
[all …]
/dragonfly/usr.bin/mail/
HDlist.c117 int tok, beg, mc, star, other, valdot, colmod, colresult; in markall() local
124 mc = 0; in markall()
139 mc++; in markall()
233 mc = 0; in markall()
238 mc++; in markall()
240 if (mc == 0) { in markall()
253 if ((np > namelist || colmod != 0) && mc == 0) in markall()
265 for (mc = 0, np = &namelist[0]; *np != NULL; np++) in markall()
268 mc++; in markall()
274 mc++; in markall()
[all …]
/dragonfly/sys/dev/misc/ecc/
HDecc_amd8000.c101 const struct ecc_amd8000_memctrl *mc; in ecc_amd8000_probe() local
107 for (mc = ecc_memctrls; mc->desc != NULL; ++mc) { in ecc_amd8000_probe()
108 if (mc->vid == vid && mc->did == did) { in ecc_amd8000_probe()
109 device_set_desc(dev, mc->desc); in ecc_amd8000_probe()
HDecc_x3400.c124 const struct ecc_x3400_memctrl *mc; in ecc_x3400_probe() local
130 for (mc = ecc_memctrls; mc->desc != NULL; ++mc) { in ecc_x3400_probe()
131 if (mc->vid == vid && mc->did == did) { in ecc_x3400_probe()
143 device_set_desc(dev, mc->desc); in ecc_x3400_probe()
/dragonfly/usr.sbin/ifmcstat/
HDifmcstat.c269 in6_multientry(struct in6_multi *mc) in in6_multientry() argument
273 KREAD(mc, &multi, struct in6_multi); in in6_multientry()
280 in6_multilist(struct in6_multi *mc) in in6_multilist() argument
282 while (mc) in in6_multilist()
283 mc = in6_multientry(mc); in in6_multilist()
/dragonfly/sys/dev/raid/vinum/
HDvinummemory.c87 struct mc malloced[MALLOCENTRIES];
92 struct mc freeinfo[FREECOUNT];
169 bcopy(&malloced[i + 1], &malloced[i], (malloccount - i) * sizeof(struct mc)); in FFree()
197 struct mc *m = (struct mc *) data; in vinum_mallocinfo()

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