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Searched refs:ira_available_class_regs (Results 1 – 8 of 8) sorted by relevance

/dragonfly/contrib/gcc-4.7/gcc/
HDira-lives.c195 && (curr_reg_pressure[cl] > ira_available_class_regs[cl])) in inc_register_pressure()
224 && curr_reg_pressure[cl] <= ira_available_class_regs[cl]) in dec_register_pressure()
238 && curr_reg_pressure[cl] <= ira_available_class_regs[cl]) in dec_register_pressure()
836 || (ira_available_class_regs[next_cl] in single_reg_class()
849 || (ira_available_class_regs[next_cl] in single_reg_class()
928 && ira_available_class_regs[cl] != 0 in ira_implicitly_set_insn_hard_regs()
929 && (ira_available_class_regs[cl] in ira_implicitly_set_insn_hard_regs()
1094 <= ira_available_class_regs[cl]); in process_bb_node_lives()
HDira.h98 #define ira_available_class_regs \ macro
HDira.c499 memset (ira_available_class_regs, 0, sizeof (ira_available_class_regs)); in setup_available_class_regs()
506 ira_available_class_regs[i]++; in setup_available_class_regs()
802 if (ira_available_class_regs[cl] == 0) in setup_pressure_classes()
804 if (ira_available_class_regs[cl] != 1 in setup_pressure_classes()
1507 if (ira_reg_class_max_nregs[cl1][mode] > ira_available_class_regs[cl1]) in ira_init_register_move_cost()
HDira-emit.c609 <= ira_available_class_regs[pclass]) in change_loop()
HDira-build.c1828 if (node->reg_pressure[pclass] > ira_available_class_regs[pclass] in low_pressure_loop_node_p()
1829 && ira_available_class_regs[pclass] > 1) in low_pressure_loop_node_p()
HDloop-invariant.c1213 > ira_available_class_regs[pressure_class]) in gain_for_invariant()
HDhaifa-sched.c1075 curr_reg_pressure[cl] - ira_available_class_regs[cl]); in print_curr_reg_pressure()
1620 before = MAX (0, max_reg_pressure[i] - ira_available_class_regs[cl]); in setup_insn_reg_pressure_info()
1622 - ira_available_class_regs[cl]); in setup_insn_reg_pressure_info()
HDira-color.c2769 <= ira_available_class_regs[pclass])) in color_pass()
2822 <= ira_available_class_regs[pclass])) in color_pass()