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Searched refs:dividers (Results 1 – 25 of 40) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
HDrv740_dpm.c125 struct atom_clock_dividers dividers; in rv740_populate_sclk_value() local
138 engine_clock, false, &dividers); in rv740_populate_sclk_value()
142 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
144 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
149 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
150 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
161 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
200 struct atom_clock_dividers dividers; in rv740_populate_mclk_value() local
206 memory_clock, false, &dividers); in rv740_populate_mclk_value()
210 ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in rv740_populate_mclk_value()
[all …]
HDrv730_dpm.c45 struct atom_clock_dividers dividers; in rv730_populate_sclk_value() local
58 engine_clock, false, &dividers); in rv730_populate_sclk_value()
62 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
64 if (dividers.enable_post_div) in rv730_populate_sclk_value()
65 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
66 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
75 if (dividers.enable_post_div) in rv730_populate_sclk_value()
80 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
81 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
82 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
[all …]
HDrv6xx_dpm.c143 struct atom_clock_dividers dividers; in rv6xx_convert_clock_to_stepping() local
146 clock, false, &dividers); in rv6xx_convert_clock_to_stepping()
150 if (dividers.enable_post_div) in rv6xx_convert_clock_to_stepping()
151 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
527 struct atom_clock_dividers *dividers, in rv6xx_calculate_vco_frequency() argument
530 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
531 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
554 struct atom_clock_dividers dividers; in rv6xx_program_engine_spread_spectrum() local
561 …if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0) { in rv6xx_program_engine_spread_spectrum()
562 vco_freq = rv6xx_calculate_vco_frequency(ref_clk, &dividers, in rv6xx_program_engine_spread_spectrum()
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HDrv770_dpm.c325 … struct atom_clock_dividers *dividers, in rv770_calculate_fractional_mpll_feedback_divider() argument
337 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
338 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
407 struct atom_clock_dividers dividers; in rv770_populate_mclk_value() local
415 memory_clock, false, &dividers); in rv770_populate_mclk_value()
419 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
424 &dividers, &clkf, &clkfrac); in rv770_populate_mclk_value()
426 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
437 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
443 if (dividers.vco_mode) in rv770_populate_mclk_value()
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HDcypress_dpm.c494 struct atom_clock_dividers dividers; in cypress_populate_mclk_value() local
501 memory_clock, strobe_mode, &dividers); in cypress_populate_mclk_value()
509 dividers.post_div = 1; in cypress_populate_mclk_value()
512 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in cypress_populate_mclk_value()
519 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
520 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in cypress_populate_mclk_value()
521 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
522 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); in cypress_populate_mclk_value()
525 if (dividers.vco_mode) in cypress_populate_mclk_value()
536 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
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HDrs780_dpm.c77 struct atom_clock_dividers dividers; in rs780_initialize_dpm_power_state() local
82 default_state->sclk_low, false, &dividers); in rs780_initialize_dpm_power_state()
86 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
87 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
88 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
90 if (dividers.enable_post_div) in rs780_initialize_dpm_power_state()
1032 struct atom_clock_dividers dividers; in rs780_dpm_force_performance_level() local
1043 ps->sclk_high, false, &dividers); in rs780_dpm_force_performance_level()
1047 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1050 ps->sclk_low, false, &dividers); in rs780_dpm_force_performance_level()
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HDradeon_atombios.c2820 struct atom_clock_dividers *dividers) in radeon_atom_get_clock_dividers() argument
2827 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in radeon_atom_get_clock_dividers()
2840 dividers->post_div = args.v1.ucPostDiv; in radeon_atom_get_clock_dividers()
2841 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2842 dividers->enable_post_div = true; in radeon_atom_get_clock_dividers()
2854 dividers->post_div = args.v2.ucPostDiv; in radeon_atom_get_clock_dividers()
2855 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2856 dividers->ref_div = args.v2.ucAction; in radeon_atom_get_clock_dividers()
2858 … dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? in radeon_atom_get_clock_dividers()
2860 … dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; in radeon_atom_get_clock_dividers()
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HDni_dpm.c2002 struct atom_clock_dividers dividers; in ni_calculate_sclk_params() local
2016 engine_clock, false, &dividers); in ni_calculate_sclk_params()
2020 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()
2023 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()
2028 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in ni_calculate_sclk_params()
2029 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in ni_calculate_sclk_params()
2040 u32 vco_freq = engine_clock * dividers.post_div; in ni_calculate_sclk_params()
2175 struct atom_clock_dividers dividers; in ni_populate_mclk_value() local
2182 memory_clock, strobe_mode, &dividers); in ni_populate_mclk_value()
2190 dividers.post_div = 1; in ni_populate_mclk_value()
[all …]
HDkv_dpm.c534 struct atom_clock_dividers dividers; in kv_set_divider_value() local
538 sclk, false, &dividers); in kv_set_divider_value()
542 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
819 struct atom_clock_dividers dividers; in kv_populate_uvd_table() local
842 … table->entries[i].vclk, false, &dividers); in kv_populate_uvd_table()
845 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
848 … table->entries[i].dclk, false, &dividers); in kv_populate_uvd_table()
851 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
892 struct atom_clock_dividers dividers; in kv_populate_vce_table() local
910 … table->entries[i].evclk, false, &dividers); in kv_populate_vce_table()
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/dragonfly/sys/dev/drm/amd/display/modules/color/
HDcolor_gamma.c237 struct dividers { struct
795 struct dividers dividers) in scale_gamma() argument
831 dividers.divider1); in scale_gamma()
833 dividers.divider1); in scale_gamma()
835 dividers.divider1); in scale_gamma()
840 dividers.divider2); in scale_gamma()
842 dividers.divider2); in scale_gamma()
844 dividers.divider2); in scale_gamma()
849 dividers.divider3); in scale_gamma()
851 dividers.divider3); in scale_gamma()
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/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
HDppatomctrl.c351 pp_atomctrl_clock_dividers_kong *dividers) in atomctrl_get_engine_pll_dividers_kong() argument
364 dividers->pll_post_divider = pll_parameters.ucPostDiv; in atomctrl_get_engine_pll_dividers_kong()
365 dividers->real_clock = le32_to_cpu(pll_parameters.ulClock); in atomctrl_get_engine_pll_dividers_kong()
374 pp_atomctrl_clock_dividers_vi *dividers) in atomctrl_get_engine_pll_dividers_vi() argument
388 dividers->pll_post_divider = in atomctrl_get_engine_pll_dividers_vi()
390 dividers->real_clock = in atomctrl_get_engine_pll_dividers_vi()
393 dividers->ul_fb_div.ul_fb_div_frac = in atomctrl_get_engine_pll_dividers_vi()
395 dividers->ul_fb_div.ul_fb_div = in atomctrl_get_engine_pll_dividers_vi()
398 dividers->uc_pll_ref_div = in atomctrl_get_engine_pll_dividers_vi()
400 dividers->uc_pll_post_div = in atomctrl_get_engine_pll_dividers_vi()
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HDppatomctrl.h300 …dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
301 …dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
310 … pp_atomctrl_clock_dividers_kong *dividers);
315 …dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
HDppatomfwctrl.c248 struct pp_atomfwctrl_clock_dividers_soc15 *dividers) in pp_atomfwctrl_get_gpu_pll_dividers_vega10() argument
266 dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
267 dividers->ulDid = le32_to_cpu(pll_output->dfs_did); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
268 dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
269 dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
270 dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
271 dividers->ucPll_ss_enable = pll_output->pll_ss_enable; in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
HDsmu8_hwmgr.c441 pp_atomctrl_clock_dividers_kong dividers; in smu8_upload_pptable_to_smu() local
486 &dividers); in smu8_upload_pptable_to_smu()
489 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
503 &dividers); in smu8_upload_pptable_to_smu()
506 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
517 &dividers); in smu8_upload_pptable_to_smu()
520 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
529 &dividers); in smu8_upload_pptable_to_smu()
532 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
543 &dividers); in smu8_upload_pptable_to_smu()
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HDvega10_hwmgr.c1457 struct pp_atomfwctrl_clock_dividers_soc15 dividers; in vega10_populate_single_lclk_level() local
1462 lclock, &dividers), in vega10_populate_single_lclk_level()
1466 *curr_lclk_did = dividers.ulDid; in vega10_populate_single_lclk_level()
1525 struct pp_atomfwctrl_clock_dividers_soc15 dividers; in vega10_populate_single_gfx_level() local
1554 gfx_clock, &dividers), in vega10_populate_single_gfx_level()
1560 cpu_to_le32(dividers.ulPll_fb_mult); in vega10_populate_single_gfx_level()
1562 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; in vega10_populate_single_gfx_level()
1564 cpu_to_le32(dividers.ulPll_ss_fbsmult); in vega10_populate_single_gfx_level()
1566 cpu_to_le16(dividers.usPll_ss_slew_frac); in vega10_populate_single_gfx_level()
1567 current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); in vega10_populate_single_gfx_level()
[all …]
/dragonfly/sys/dev/drm/amd/amdgpu/
HDamdgpu_atombios.c999 struct atom_clock_dividers *dividers) in amdgpu_atombios_get_clock_dividers() argument
1006 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in amdgpu_atombios_get_clock_dividers()
1022 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1023 dividers->enable_post_div = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1025 dividers->enable_dithen = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1027 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); in amdgpu_atombios_get_clock_dividers()
1028 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); in amdgpu_atombios_get_clock_dividers()
1029 dividers->ref_div = args.v3.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1030 dividers->vco_mode = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1042 dividers->post_div = args.v5.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
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HDvi.c722 struct atom_clock_dividers dividers; in vi_set_uvd_clock() local
727 clock, false, &dividers); in vi_set_uvd_clock()
738 tmp |= dividers.post_divider; in vi_set_uvd_clock()
792 struct atom_clock_dividers dividers; in vi_set_vce_clocks() local
813 ecclk, false, &dividers); in vi_set_vce_clocks()
828 tmp |= dividers.post_divider; in vi_set_vce_clocks()
HDcik.c1302 struct atom_clock_dividers dividers; in cik_set_uvd_clock() local
1307 clock, false, &dividers); in cik_set_uvd_clock()
1314 tmp |= dividers.post_divider; in cik_set_uvd_clock()
1343 struct atom_clock_dividers dividers; in cik_set_vce_clocks() local
1348 ecclk, false, &dividers); in cik_set_vce_clocks()
1363 tmp |= dividers.post_divider; in cik_set_vce_clocks()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
HDvegam_smumgr.c724 struct pp_atomctrl_clock_dividers_ai dividers; in vegam_calculate_sclk_params() local
733 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers); in vegam_calculate_sclk_params()
735 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()
736 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()
737 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in vegam_calculate_sclk_params()
738 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()
740 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in vegam_calculate_sclk_params()
742 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()
743 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in vegam_calculate_sclk_params()
744 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; in vegam_calculate_sclk_params()
[all …]
HDpolaris10_smumgr.c845 struct pp_atomctrl_clock_dividers_ai dividers; in polaris10_calculate_sclk_params() local
854 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers); in polaris10_calculate_sclk_params()
856 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in polaris10_calculate_sclk_params()
857 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in polaris10_calculate_sclk_params()
858 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in polaris10_calculate_sclk_params()
859 sclk_setting->PllRange = dividers.ucSclkPllRange; in polaris10_calculate_sclk_params()
861 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in polaris10_calculate_sclk_params()
863 sclk_setting->SSc_En = dividers.ucSscEnable; in polaris10_calculate_sclk_params()
864 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in polaris10_calculate_sclk_params()
865 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; in polaris10_calculate_sclk_params()
[all …]
HDfiji_smumgr.c871 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_calculate_sclk_params() local
883 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers); in fiji_calculate_sclk_params()
891 ref_divider = 1 + dividers.uc_pll_ref_div; in fiji_calculate_sclk_params()
894 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in fiji_calculate_sclk_params()
898 SPLL_REF_DIV, dividers.uc_pll_ref_div); in fiji_calculate_sclk_params()
900 SPLL_PDIV_A, dividers.uc_pll_post_div); in fiji_calculate_sclk_params()
914 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in fiji_calculate_sclk_params()
943 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in fiji_calculate_sclk_params()
1316 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_populate_smc_acpi_level() local
1347 table->ACPILevel.SclkFrequency, &dividers); in fiji_populate_smc_acpi_level()
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HDtonga_smumgr.c532 pp_atomctrl_clock_dividers_vi dividers; in tonga_calculate_sclk_params() local
544 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers); in tonga_calculate_sclk_params()
552 reference_divider = 1 + dividers.uc_pll_ref_div; in tonga_calculate_sclk_params()
555 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in tonga_calculate_sclk_params()
559 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
561 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
575 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in tonga_calculate_sclk_params()
601 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in tonga_calculate_sclk_params()
1170 struct pp_atomctrl_clock_dividers_vi dividers; in tonga_populate_smc_acpi_level() local
1189 table->ACPILevel.SclkFrequency, &dividers); in tonga_populate_smc_acpi_level()
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HDci_smumgr.c299 struct pp_atomctrl_clock_dividers_vi dividers; in ci_calculate_sclk_params() local
311 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers); in ci_calculate_sclk_params()
319 ref_divider = 1 + dividers.uc_pll_ref_div; in ci_calculate_sclk_params()
322 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in ci_calculate_sclk_params()
326 SPLL_REF_DIV, dividers.uc_pll_ref_div); in ci_calculate_sclk_params()
328 SPLL_PDIV_A, dividers.uc_pll_post_div); in ci_calculate_sclk_params()
341 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in ci_calculate_sclk_params()
364 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in ci_calculate_sclk_params()
1379 struct pp_atomctrl_clock_dividers_vi dividers; in ci_populate_smc_acpi_level() local
1402 table->ACPILevel.SclkFrequency, &dividers); in ci_populate_smc_acpi_level()
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HDiceland_smumgr.c799 pp_atomctrl_clock_dividers_vi dividers; in iceland_calculate_sclk_params() local
811 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers); in iceland_calculate_sclk_params()
819 reference_divider = 1 + dividers.uc_pll_ref_div; in iceland_calculate_sclk_params()
822 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in iceland_calculate_sclk_params()
826 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in iceland_calculate_sclk_params()
828 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in iceland_calculate_sclk_params()
842 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in iceland_calculate_sclk_params()
868 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in iceland_calculate_sclk_params()
1426 struct pp_atomctrl_clock_dividers_vi dividers; in iceland_populate_smc_acpi_level() local
1450 table->ACPILevel.SclkFrequency, &dividers); in iceland_populate_smc_acpi_level()
[all …]
/dragonfly/sys/bus/u4b/serial/
HDuchcom.c183 static const struct uchcom_divider_record dividers[] = variable
539 for (i = 0; i != NELEM(dividers); i++) { in uchcom_calc_divider_settings()
540 if (dividers[i].dvr_high >= rate && in uchcom_calc_divider_settings()
541 dividers[i].dvr_low <= rate) { in uchcom_calc_divider_settings()
542 rp = &dividers[i]; in uchcom_calc_divider_settings()

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