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Searched refs:dcc (Results 1 – 16 of 16) sorted by relevance

/dragonfly/sys/dev/drm/i915/
HDi915_gem_fence_reg.c609 uint32_t dcc; in i915_gem_detect_bit_6_swizzle() local
619 dcc = I915_READ(DCC); in i915_gem_detect_bit_6_swizzle()
620 switch (dcc & DCC_ADDRESSING_MODE_MASK) { in i915_gem_detect_bit_6_swizzle()
627 if (dcc & DCC_CHANNEL_XOR_DISABLE) { in i915_gem_detect_bit_6_swizzle()
633 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { in i915_gem_detect_bit_6_swizzle()
652 if (dcc == 0xffffffff) { in i915_gem_detect_bit_6_swizzle()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
HDdcn10_hubp.c159 struct dc_plane_dcc_param *dcc) in hubp1_program_size() argument
172 meta_pitch = dcc->video.meta_pitch_l - 1; in hubp1_program_size()
174 meta_pitch_c = dcc->video.meta_pitch_c - 1; in hubp1_program_size()
177 meta_pitch = dcc->grph.meta_pitch - 1; in hubp1_program_size()
182 if (!dcc->enable) { in hubp1_program_size()
487 struct dc_plane_dcc_param *dcc, in hubp1_program_surface_config() argument
490 hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); in hubp1_program_surface_config()
492 hubp1_program_size(hubp, format, plane_size, dcc); in hubp1_program_surface_config()
HDdcn10_hubp.h666 struct dc_plane_dcc_param *dcc,
686 struct dc_plane_dcc_param *dcc);
HDdcn10_hw_sequencer.c2103 &plane_state->dcc, in update_dchubp_dpp()
/dragonfly/sys/dev/drm/amd/display/dc/inc/hw/
HDhubp.h98 struct dc_plane_dcc_param *dcc,
HDmem_input.h154 struct dc_plane_dcc_param *dcc,
/dragonfly/sys/dev/drm/amd/display/dc/
HDdc.h479 struct dc_plane_dcc_param dcc; member
519 struct dc_plane_dcc_param dcc; member
/dragonfly/sys/dev/drm/amd/display/dc/core/
HDdc.c1139 if (u->plane_info->dcc.enable != u->surface->dcc.enable in get_plane_info_update_type()
1140 … || u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks in get_plane_info_update_type()
1141 … || u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch) in get_plane_info_update_type()
HDdc_debug.c165 plane_state->dcc.enable, in pre_surface_trace()
/dragonfly/sys/dev/drm/amd/display/dc/dml/
HDdisplay_mode_structs.h193 unsigned char dcc; member
HDdml1_display_rq_dlg_calc.c1182 dcc_en = e2e_pipe_param.pipe.src.dcc; in dml1_rq_dlg_get_dlg_params()
/dragonfly/sys/dev/drm/amd/display/dc/calcs/
HDdcn_calcs.c259 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0; in pipe_ctx_to_e2e_pipe_params()
269 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
273 input->src.meta_pitch = pipe->plane_state->dcc.grph.meta_pitch; in pipe_ctx_to_e2e_pipe_params()
918 … v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; in dcn_validate_bandwidth()
/dragonfly/nrelease/gui/root/.irssi/
HDconfig61 CHAT = "dcc chat";
/dragonfly/sys/dev/drm/amd/display/dc/dce/
HDdce_mem_input.c510 struct dc_plane_dcc_param *dcc, in dce_mi_program_surface_config() argument
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
HDdce110_mem_input_v.c648 struct dc_plane_dcc_param *dcc, in dce_mem_input_v_program_surface_config() argument
/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/
HDamdgpu_dm.c4245 plane_info[i].dcc = plane_states[i]->dcc; in commit_planes_to_stream()