Searched refs:cik (Results 1 – 6 of 6) sorted by relevance
2350 u32 *tile = rdev->config.cik.tile_mode_array; in cik_tiling_mode_table_init()2351 u32 *macrotile = rdev->config.cik.macrotile_mode_array; in cik_tiling_mode_table_init()2353 ARRAY_SIZE(rdev->config.cik.tile_mode_array); in cik_tiling_mode_table_init()2355 ARRAY_SIZE(rdev->config.cik.macrotile_mode_array); in cik_tiling_mode_table_init()2358 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init()2359 rdev->config.cik.max_shader_engines; in cik_tiling_mode_table_init()2361 switch (rdev->config.cik.mem_row_size_in_kb) { in cik_tiling_mode_table_init()2374 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()3160 rdev->config.cik.backend_enable_mask = enabled_rbs; in cik_setup_rb()3211 rdev->config.cik.max_shader_engines = 2; in cik_gpu_init()[all …]
331 *value = rdev->config.cik.tile_config; in radeon_info_ioctl()385 *value = rdev->config.cik.max_backends_per_se * in radeon_info_ioctl()386 rdev->config.cik.max_shader_engines; in radeon_info_ioctl()405 *value = rdev->config.cik.max_tile_pipes; in radeon_info_ioctl()425 *value = rdev->config.cik.backend_map; in radeon_info_ioctl()454 *value = rdev->config.cik.max_cu_per_sh; in radeon_info_ioctl()480 *value = rdev->config.cik.max_shader_engines; in radeon_info_ioctl()492 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()527 value = rdev->config.cik.tile_mode_array; in radeon_info_ioctl()539 value = rdev->config.cik.macrotile_mode_array; in radeon_info_ioctl()[all …]
73 cik.c \
1293 … num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; in dce4_crtc_do_set_base()1349 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base()
803 struct cik_irq_stat_regs cik; member2210 struct cik_asic cik; member
2493 dev/drm/radeon/cik.c optional radeon drm compile-with "${NORMAL_C} -in…