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Searched refs:cfg1 (Results 1 – 16 of 16) sorted by relevance

/dragonfly/sys/dev/disk/nata/chipsets/
HData-jmicron.c98 if (ctlr->chip->cfg1 && (error = ata_ahci_chipinit(dev))) { in ata_jmicron_chipinit()
109 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2; in ata_jmicron_chipinit()
121 if (ch->unit >= ctlr->chip->cfg1) { in ata_jmicron_allocate()
122 ch->unit -= ctlr->chip->cfg1; in ata_jmicron_allocate()
124 ch->unit += ctlr->chip->cfg1; in ata_jmicron_allocate()
137 if (ch->unit >= ctlr->chip->cfg1) in ata_jmicron_reset()
149 if (ch->unit >= ctlr->chip->cfg1) in ata_jmicron_dmainit()
161 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) { in ata_jmicron_setmode()
HData-highpoint.c69 if (idx->cfg1 == HPT_374) { in ata_highpoint_ident()
103 if (ctlr->chip->cfg1 < HPT_372) in ata_highpoint_chipinit()
157 if (ctlr->chip->cfg1 == HPT_366 && ata_atapi(dev)) in ata_highpoint_setmode()
174 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_highpoint_setmode()
186 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(gparent) == 1) { in ata_highpoint_check_80pin()
HData-nvidia.c153 if (ctlr->chip->cfg1 & NVAHCI) in ata_nvidia_ident()
176 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_chipinit()
185 if (ctlr->chip->cfg1 & NVQ) { in ata_nvidia_chipinit()
247 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_status()
248 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); in ata_nvidia_status()
252 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
262 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
HData-sis.c98 id[0].cfg1 = SIS_133NEW; in ata_sis_ident()
112 id[0].cfg1 = SIS_133OLD; in ata_sis_ident()
115 id[0].cfg1 = SIS_100NEW; in ata_sis_ident()
142 switch (ctlr->chip->cfg1) { in ata_sis_chipinit()
222 if (ctlr->chip->cfg1 == SIS_133NEW) { in ata_sis_setmode()
244 switch (ctlr->chip->cfg1) { in ata_sis_setmode()
HData-via.c200 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); in ata_via_allocate()
202 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); in ata_via_allocate()
204 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); in ata_via_allocate()
286 if (ctlr->chip->cfg1 != VIA133) in ata_via_old_setmode()
290 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); in ata_via_old_setmode()
HData-amd.c70 if (ctlr->chip->cfg1 & AMD_BUG) in ata_amd_chipinit()
97 if (ctlr->chip->cfg1 & AMD_CABLE) { in ata_amd_setmode()
HData-ati.c74 switch (ctlr->chip->cfg1) { in ata_ati_ident()
108 if (ctlr->chip->cfg1 & ATI_AHCI) { in ata_ati_chipinit()
HData-serverworks.c80 if (ctlr->chip->cfg1 == SWKS_MIO) { in ata_serverworks_chipinit()
94 else if (ctlr->chip->cfg1 == SWKS_33) { in ata_serverworks_chipinit()
114 ((ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02), 1); in ata_serverworks_chipinit()
HData-acard.c74 if (ctlr->chip->cfg1 == ATP_OLD) { in ata_acard_chipinit()
102 if (ctlr->chip->cfg1 == ATP_OLD && in ata_acard_status()
HData-marvell.c120 ctlr->channels = ctlr->chip->cfg1; in ata_marvell_pata_chipinit()
178 ctlr->channels = ctlr->chip->cfg1; in ata_marvell_edma_chipinit()
182 if (ctlr->chip->cfg1 > 4) in ata_marvell_edma_chipinit()
HData-intel.c177 if ((ctlr->chip->cfg1 == INTEL_AHCI) && in ata_intel_chipinit()
229 if (ctlr->chip->cfg1) { in ata_intel_reset()
HData-promise.c196 switch (ctlr->chip->cfg1) { in ata_promise_chipinit()
449 switch (ctlr->chip->cfg1) { in ata_promise_setmode()
488 if (ctlr->chip->cfg1 < PR_TX) in ata_promise_setmode()
490 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_promise_setmode()
HData-acerlabs.c79 ctlr->channels = ctlr->chip->cfg1; in ata_ali_chipinit()
HData-siliconimage.c98 switch (ctlr->chip->cfg1) { in ata_sii_chipinit()
/dragonfly/sys/dev/drm/i915/
HDintel_dsi_vbt.c252 u16 cfg0, cfg1; in chv_exec_gpio() local
290 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); in chv_exec_gpio()
293 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); in chv_exec_gpio()
/dragonfly/sys/dev/disk/nata/
HData-pci.h38 int cfg1; member