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Searched refs:caps (Results 1 – 25 of 133) sorted by relevance

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/dragonfly/sys/kern/
HDkern_caps.c68 elm = cred->cr_caps.caps[__SYSCAP_INDEX(cap)]; in caps_check_cred()
125 res = (int)(cred->cr_caps.caps[__SYSCAP_INDEX(cap)] >> in sys_syscap_get()
186 res = (int)(cred->cr_caps.caps[__SYSCAP_INDEX(cap)] >> in sys_syscap_set()
202 atomic_set_64(&cred->cr_caps.caps[0], anymask); in sys_syscap_set()
203 atomic_set_64(&cred->cr_caps.caps[ __SYSCAP_INDEX(cap)], in sys_syscap_set()
243 elm = cred->cr_caps.caps[i]; in caps_exec()
246 if (elm != cred->cr_caps.caps[i]) in caps_exec()
257 elm = cred->cr_caps.caps[i]; in caps_exec()
260 cred->cr_caps.caps[i] = elm; in caps_exec()
276 res = (int)(cred->cr_caps.caps[__SYSCAP_INDEX(cap)] >> in caps_get()
[all …]
HDkern_cputimer.c334 if ((cti->caps & cputimer_intr_caps) == cputimer_intr_caps) { in cputimer_intr_select()
418 cputimer_intr_select_caps(uint32_t caps) in cputimer_intr_select_caps() argument
425 if ((cti->caps & caps) == caps) { in cputimer_intr_select_caps()
438 cputimer_intr_caps = caps; in cputimer_intr_select_caps()
/dragonfly/sys/dev/drm/amd/display/modules/freesync/
HDfreesync.c122 struct mod_freesync_caps *caps; member
255 struct dc_stream_state *stream, struct mod_freesync_caps *caps) in mod_freesync_add_stream() argument
285 core_freesync->map[core_freesync->num_entities].caps = caps; in mod_freesync_add_stream()
313 } else if (caps->supported && (core_freesync->opts.lcd_freesync_default_set)) { in mod_freesync_add_stream()
333 if (caps->supported && in mod_freesync_add_stream()
334 nom_refresh_rate_uhz >= caps->min_refresh_in_micro_hz && in mod_freesync_add_stream()
335 nom_refresh_rate_uhz <= caps->max_refresh_in_micro_hz) in mod_freesync_add_stream()
395 ctx->supported = core_freesync->map[index].caps->supported; in update_stream_freesync_context()
403 core_freesync->map[index].caps->min_refresh_in_micro_hz; in update_stream_freesync_context()
413 if (core_freesync->map[index].caps->supported) { in update_stream()
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/dragonfly/sys/dev/sound/pcm/
HDvchan.c55 struct pcmchan_caps caps; member
89 info->caps.fmtlist = info->fmtlist + in vchan_init()
117 if (!snd_fmtvalid(format, info->caps.fmtlist)) in vchan_setformat()
132 return (info->caps.maxspeed); in vchan_setspeed()
201 info->caps.fmtlist = info->fmtlist; in vchan_getcaps()
203 for (i = 0; info->caps.fmtlist[i] != 0; i++) { in vchan_getcaps()
204 if (info->caps.fmtlist[i] & AFMT_PASSTHROUGH) in vchan_getcaps()
208 info->caps.fmtlist[i] = pformat; in vchan_getcaps()
211 info->caps.minspeed = c->speed; in vchan_getcaps()
213 info->caps.minspeed = pspeed; in vchan_getcaps()
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HDfeeder_chain.c569 struct pcmchan_caps *caps; in feeder_chain() local
613 caps = chn_getcaps(c); in feeder_chain()
614 if (caps == NULL || caps->fmtlist == NULL) { in feeder_chain()
621 !snd_fmtvalid(c->format, caps->fmtlist)) in feeder_chain()
624 hwfmt = snd_fmtbest(c->format, caps->fmtlist); in feeder_chain()
625 if (hwfmt == 0 || !snd_fmtvalid(hwfmt, caps->fmtlist)) { in feeder_chain()
631 for (i = 0; caps->fmtlist[i] != 0; i++) in feeder_chain()
632 kprintf("0x%08x\n", caps->fmtlist[i]); in feeder_chain()
HDchannel.c1520 struct pcmchan_caps *caps; in chn_oss_getmask() local
1527 caps = chn_getcaps(c); in chn_oss_getmask()
1528 if (caps == NULL || caps->fmtlist == NULL) in chn_oss_getmask()
1531 for (i = 0; caps->fmtlist[i] != 0; i++) { in chn_oss_getmask()
1532 format = caps->fmtlist[i]; in chn_oss_getmask()
1968 struct pcmchan_caps *caps; in chn_setparam() local
1980 caps = chn_getcaps(c); in chn_setparam()
1983 RANGE(hwspeed, caps->minspeed, caps->maxspeed); in chn_setparam()
2280 struct pcmchan_caps *caps; in chn_notify() local
2360 caps = chn_getcaps(c); in chn_notify()
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HDac97.c63 unsigned count, caps, se, extcaps, extid, extstat, noext:1; member
411 return codec->caps; in ac97_getcaps()
560 codec->caps |= AC97_CAP_TONE; in ac97_fix_tone()
571 if ((codec->caps & AC97_CAP_TONE) == 0) { in ac97_fix_tone()
632 codec->caps = i & 0x03ff; in ac97_initmixer()
763 if (codec->caps & (1 << i)) in ac97_initmixer()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDamdgpu_virt.h239 uint32_t caps; member
257 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
260 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
263 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
266 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
269 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
HDnbio_v6_1.c252 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; in nbio_v6_1_detect_hw_virt()
255 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; in nbio_v6_1_detect_hw_virt()
259 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; in nbio_v6_1_detect_hw_virt()
HDamdgpu_virt.c264 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_request_full_gpu()
287 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_release_full_gpu()
308 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_reset_gpu()
/dragonfly/sys/dev/drm/amd/display/dc/dce80/
HDdce80_resource.c820 dc->caps.max_downscale_ratio = 200; in dce80_construct()
821 dc->caps.i2c_speed_in_khz = 40; in dce80_construct()
822 dc->caps.max_cursor_size = 128; in dce80_construct()
823 dc->caps.dual_link_dvi = true; in dce80_construct()
956 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
957 dc->caps.disable_dp_clk_share = true; in dce80_construct()
1013 dc->caps.max_downscale_ratio = 200; in dce81_construct()
1014 dc->caps.i2c_speed_in_khz = 40; in dce81_construct()
1015 dc->caps.max_cursor_size = 128; in dce81_construct()
1016 dc->caps.is_apu = true; in dce81_construct()
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/dragonfly/sys/dev/disk/sdhci/
HDsdhci.c635 uint32_t caps, caps2, freq, host_caps; in sdhci_init_slot() local
653 caps = slot->caps; in sdhci_init_slot()
656 caps = RD4(slot, SDHCI_CAPABILITIES); in sdhci_init_slot()
663 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE && in sdhci_init_slot()
664 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) { in sdhci_init_slot()
670 } else if ((caps & SDHCI_SLOTTYPE_MASK) == in sdhci_init_slot()
677 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> in sdhci_init_slot()
680 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> in sdhci_init_slot()
699 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; in sdhci_init_slot()
700 if (caps & SDHCI_TIMEOUT_CLK_UNIT) in sdhci_init_slot()
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/dragonfly/sys/dev/drm/amd/powerplay/inc/
HDhardwaremanager.h281 static inline void phm_cap_set(uint32_t *caps, in phm_cap_set() argument
284 caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL << in phm_cap_set()
288 static inline void phm_cap_unset(uint32_t *caps, in phm_cap_unset() argument
291 …caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); in phm_cap_unset()
294 static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c) in phm_cap_enabled() argument
296 return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] & in phm_cap_enabled()
/dragonfly/sys/bus/u4b/input/
HDwsp.c245 uint8_t caps; /* device capability bitmask */ member
262 .caps = 0,
277 .caps = 0,
292 .caps = HAS_INTEGRATED_BUTTON,
307 .caps = HAS_INTEGRATED_BUTTON,
322 .caps = HAS_INTEGRATED_BUTTON,
337 .caps = HAS_INTEGRATED_BUTTON,
352 .caps = HAS_INTEGRATED_BUTTON,
367 .caps = HAS_INTEGRATED_BUTTON,
382 .caps = HAS_INTEGRATED_BUTTON,
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/dragonfly/sys/dev/drm/i915/
HDintel_sdvo.c86 struct intel_sdvo_caps caps; member
1633 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) in intel_sdvo_get_capabilities() argument
1635 BUILD_BUG_ON(sizeof(*caps) != 8); in intel_sdvo_get_capabilities()
1638 caps, sizeof(*caps))) in intel_sdvo_get_capabilities()
1654 caps->vendor_id, in intel_sdvo_get_capabilities()
1655 caps->device_id, in intel_sdvo_get_capabilities()
1656 caps->device_rev_id, in intel_sdvo_get_capabilities()
1657 caps->sdvo_version_major, in intel_sdvo_get_capabilities()
1658 caps->sdvo_version_minor, in intel_sdvo_get_capabilities()
1659 caps->sdvo_inputs_mask, in intel_sdvo_get_capabilities()
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HDi915_vgpu.c78 dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps)); in i915_check_vgpu()
86 return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT; in intel_vgpu_has_full_48bit_ppgtt()
/dragonfly/sys/dev/sound/pci/
HDes137x.c140 struct pcmchan_caps caps; member
481 ch->caps = es_caps; in eschan_init()
484 ch->caps.maxspeed = ES1370_DAC1_MAXSPEED; in eschan_init()
485 ch->caps.minspeed = ES1370_DAC1_MINSPEED; in eschan_init()
490 ch->caps.maxspeed = fixed_rate; in eschan_init()
491 ch->caps.minspeed = fixed_rate; in eschan_init()
575 if (ch->caps.minspeed == ch->caps.maxspeed) { in eschan1370_setspeed()
577 return (ch->caps.maxspeed); in eschan1370_setspeed()
579 if (speed < ch->caps.minspeed) in eschan1370_setspeed()
580 speed = ch->caps.minspeed; in eschan1370_setspeed()
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/dragonfly/usr.sbin/pciconf/
HDpciconf.c68 static void list_devs(int verbose, int bars, int bridge, int caps,
95 int listmode, readmode, writemode, attachedmode, bars, caps, verbose; in main() local
100 attachedmode = bars = caps = verbose = byte = isshort = 0; in main()
119 caps = 1; in main()
158 list_devs(verbose, bars, bridge, caps, errors); in main()
175 list_devs(int verbose, int bars, int bridge, int caps, int errors) in list_devs() argument
185 fd = open(_PATH_DEVPCI, (bridge || caps || errors) ? in list_devs()
236 if (caps) in list_devs()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
HDdcn10_resource.c1069 …enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) in dcn10_validate_plane() argument
1072 && caps->max_video_width != 0 in dcn10_validate_plane()
1073 && plane_state->src_rect.width > caps->max_video_width) in dcn10_validate_plane()
1128 dc->caps.max_video_width = 3840; in construct()
1129 dc->caps.max_downscale_ratio = 200; in construct()
1130 dc->caps.i2c_speed_in_khz = 100; in construct()
1131 dc->caps.max_cursor_size = 256; in construct()
1132 dc->caps.max_slave_planes = 1; in construct()
1133 dc->caps.is_apu = true; in construct()
1134 dc->caps.post_blend_color_processing = false; in construct()
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HDdcn10_dpp_dscl.c176 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_get_dscl_mode()
209 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_set_lb()
489 dpp->base.caps->dscl_calc_lb_num_partitions( in dpp1_dscl_find_lb_memory_config()
496 dpp->base.caps->dscl_calc_lb_num_partitions( in dpp1_dscl_find_lb_memory_config()
505 dpp->base.caps->dscl_calc_lb_num_partitions( in dpp1_dscl_find_lb_memory_config()
513 dpp->base.caps->dscl_calc_lb_num_partitions( in dpp1_dscl_find_lb_memory_config()
/dragonfly/sys/dev/drm/amd/display/modules/inc/
HDmod_freesync.h104 struct dc_stream_state *stream, struct mod_freesync_caps *caps);
140 struct mod_freesync_caps *caps);
/dragonfly/sys/netproto/802_11/wlan/
HDieee80211.c96 struct ifmedia *media, int caps, int addsta,
1490 addmedia(struct ifmedia *media, int caps, int addsta, int mode, int mword) in addmedia() argument
1514 if (caps & IEEE80211_C_IBSS) in addmedia()
1516 if (caps & IEEE80211_C_HOSTAP) in addmedia()
1518 if (caps & IEEE80211_C_AHDEMO) in addmedia()
1520 if (caps & IEEE80211_C_MONITOR) in addmedia()
1522 if (caps & IEEE80211_C_WDS) in addmedia()
1524 if (caps & IEEE80211_C_MBSS) in addmedia()
1535 struct ifmedia *media, int caps, int addsta, in ieee80211_media_setup() argument
1555 addmedia(media, caps, addsta, mode, IFM_AUTO); in ieee80211_media_setup()
[all …]
/dragonfly/sys/dev/drm/amd/display/dc/dce100/
HDdce100_resource.c802 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) in dce100_validate_plane() argument
927 dc->caps.max_downscale_ratio = 200; in construct()
928 dc->caps.i2c_speed_in_khz = 40; in construct()
929 dc->caps.max_cursor_size = 128; in construct()
930 dc->caps.dual_link_dvi = true; in construct()
931 dc->caps.disable_dp_clk_share = true; in construct()
984 dc->caps.max_planes = pool->base.pipe_count; in construct()
/dragonfly/contrib/wpa_supplicant/wpa_supplicant/
HDbss.h90 u16 caps; member
166 (bss->caps & IEEE80211_CAP_DMG_MASK) == IEEE80211_CAP_DMG_PBSS; in bss_is_pbss()
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
HDdce110_resource.c884 struct dc_caps *caps) in dce110_validate_plane() argument
1081 ctx->dc->caps.max_slave_planes = 1; in underlay_create()
1082 ctx->dc->caps.max_slave_planes = 1; in underlay_create()
1177 dc->caps.max_downscale_ratio = 150; in construct()
1178 dc->caps.i2c_speed_in_khz = 100; in construct()
1179 dc->caps.max_cursor_size = 128; in construct()
1180 dc->caps.is_apu = true; in construct()
1326 dc->caps.max_planes = pool->base.pipe_count; in construct()

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