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Searched refs:asic_id (Results 1 – 21 of 21) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/inc/
HDresource.h37 struct hw_asic_id asic_id);
79 struct hw_asic_id asic_id);
HDdce_calcs.h472 struct hw_asic_id asic_id);
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
HDdce110_resource.c476 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? in dce110_hwseq_create()
1145 struct hw_asic_id *asic_id) in dce110_resource_cap() argument
1147 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev)) in dce110_resource_cap()
1157 struct hw_asic_id asic_id) in construct() argument
1167 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in construct()
1328 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); in construct()
1342 struct hw_asic_id asic_id) in dce110_create_resource_pool() argument
1350 if (construct(num_virtual_links, dc, pool, asic_id)) in dce110_create_resource_pool()
HDdce110_resource.h46 struct hw_asic_id asic_id);
HDdce110_compressor.c548 compressor->base.memory_bus_width = ctx->asic_id.vram_width; in dce110_compressor_construct()
/dragonfly/sys/dev/drm/amd/display/dc/core/
HDdc_resource.c51 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) in resource_parse_asic_id() argument
54 switch (asic_id.chip_family) { in resource_parse_asic_id()
60 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) || in resource_parse_asic_id()
61 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) || in resource_parse_asic_id()
62 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev)) in resource_parse_asic_id()
72 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) || in resource_parse_asic_id()
73 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) { in resource_parse_asic_id()
77 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || in resource_parse_asic_id()
78 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || in resource_parse_asic_id()
79 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { in resource_parse_asic_id()
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HDdc.c557 dc_ctx->asic_id = init_params->asic_id; in construct()
572 dc_version = resource_parse_asic_id(init_params->asic_id); in construct()
585 bp_init_data.bios = init_params->asic_id.atombios_base_address; in construct()
621 init_params->asic_id); in construct()
/dragonfly/sys/dev/drm/amd/display/dc/dce112/
HDdce112_resource.c1084 struct hw_asic_id *asic_id) in dce112_resource_cap() argument
1086 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || in dce112_resource_cap()
1087 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) in dce112_resource_cap()
1104 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in construct()
1276 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); in construct()
HDdce112_compressor.c810 compressor->base.memory_bus_width = ctx->asic_id.vram_width; in dce112_compressor_construct()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
HDdcn10_resource.c1211 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { in construct()
1218 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; in construct()
1228 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { in construct()
/dragonfly/sys/dev/drm/amd/display/dc/calcs/
HDdce_calcs.c46 static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asic_id) in bw_calcs_version_from_asic_id() argument
48 switch (asic_id.chip_family) { in bw_calcs_version_from_asic_id()
51 if (ASIC_REV_IS_STONEY(asic_id.hw_internal_rev)) in bw_calcs_version_from_asic_id()
56 if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) in bw_calcs_version_from_asic_id()
58 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev)) in bw_calcs_version_from_asic_id()
60 if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev)) in bw_calcs_version_from_asic_id()
62 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) in bw_calcs_version_from_asic_id()
2028 struct hw_asic_id asic_id) in bw_calcs_init() argument
2033 enum bw_calcs_version version = bw_calcs_version_from_asic_id(asic_id); in bw_calcs_init()
2041 … vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits; in bw_calcs_init()
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/dragonfly/sys/dev/drm/amd/display/dc/
HDdc_types.h83 struct hw_asic_id asic_id; member
HDdc.h338 struct hw_asic_id asic_id; member
/dragonfly/sys/dev/drm/amd/display/dc/dce120/
HDdce120_resource.c874 bool harvest_enabled = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev); in construct()
1054 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); in construct()
/dragonfly/sys/dev/drm/amd/powerplay/inc/
HDsmu71_discrete.h560 uint32_t asic_id; member
HDsmu73_discrete.h662 uint32_t asic_id; member
HDsmu74_discrete.h627 uint32_t asic_id; member
HDsmu72_discrete.h627 uint32_t asic_id; member
HDsmu75_discrete.h656 uint32_t asic_id; member
/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/
HDamdgpu_dm.c413 init_data.asic_id.chip_family = adev->family; in amdgpu_dm_init()
415 init_data.asic_id.pci_revision_id = adev->rev_id; in amdgpu_dm_init()
416 init_data.asic_id.hw_internal_rev = adev->external_rev_id; in amdgpu_dm_init()
417 init_data.asic_id.chip_id = adev->pdev->device; in amdgpu_dm_init()
419 init_data.asic_id.vram_width = adev->gmc.vram_width; in amdgpu_dm_init()
421 init_data.asic_id.atombios_base_address = in amdgpu_dm_init()
/dragonfly/sys/dev/drm/amd/display/dc/dce/
HDdce_clocks.c325 if (!ASICREV_IS_VEGA20_P(clk->ctx->asic_id.hw_internal_rev)) in dce112_set_clock()