Searched refs:__BIT (Results 1 – 11 of 11) sorted by relevance
138 #define NVMM_CAP_ARCH_VCPU_CONF_CPUID __BIT(0)139 #define NVMM_CAP_ARCH_VCPU_CONF_TPR __BIT(1)228 #undef __BIT229 #define __BIT(__n) __BIT64(__n) macro374 #define CPUID_0_01_ECX_SSE3 __BIT(0)375 #define CPUID_0_01_ECX_PCLMULQDQ __BIT(1)376 #define CPUID_0_01_ECX_DTES64 __BIT(2)377 #define CPUID_0_01_ECX_MONITOR __BIT(3)378 #define CPUID_0_01_ECX_DS_CPL __BIT(4)379 #define CPUID_0_01_ECX_VMX __BIT(5)[all …]
188 #define IA32_FEATURE_CONTROL_LOCK __BIT(0)189 #define IA32_FEATURE_CONTROL_IN_SMX __BIT(1)190 #define IA32_FEATURE_CONTROL_OUT_SMX __BIT(2)195 #define IA32_VMX_BASIC_MEM_WIDTH __BIT(48)196 #define IA32_VMX_BASIC_DUAL __BIT(49)200 #define IA32_VMX_BASIC_IO_REPORT __BIT(54)201 #define IA32_VMX_BASIC_TRUE_CTLS __BIT(55)220 #define IA32_VMX_EPT_VPID_XO __BIT(0)221 #define IA32_VMX_EPT_VPID_WALKLENGTH_4 __BIT(6)222 #define IA32_VMX_EPT_VPID_UC __BIT(8)[all …]
239 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x)240 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x)243 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x)244 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x)247 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x)250 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0)251 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1)252 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2)253 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3)254 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4)[all …]
99 #define ET_PM_SYSCLK_GATE __BIT(3)100 #define ET_PM_TXCLK_GATE __BIT(4)101 #define ET_PM_RXCLK_GATE __BIT(5)107 #define ET_SWRST_TXDMA __BIT(0)108 #define ET_SWRST_RXDMA __BIT(1)109 #define ET_SWRST_TXMAC __BIT(2)110 #define ET_SWRST_RXMAC __BIT(3)111 #define ET_SWRST_MAC __BIT(4)112 #define ET_SWRST_MAC_STAT __BIT(5)113 #define ET_SWRST_MMC __BIT(6)[all …]
81 #define ET_TDCTRL2_LAST_FRAG __BIT(0)82 #define ET_TDCTRL2_FIRST_FRAG __BIT(1)83 #define ET_TDCTRL2_INTR __BIT(2)108 #define ET_RXS_STATRING_WRAP __BIT(28)
22 #define PCI_E3_ERRSTS_DMERR __BIT(1)23 #define PCI_E3_ERRSTS_DSERR __BIT(0)27 #define PCI_CORE_CAPID0_A_ECCDIS __BIT(25)52 #define MCH_E3_ERRLOG0_CERRSTS __BIT(0)53 #define MCH_E3_ERRLOG0_MERRSTS __BIT(1)68 #define MCH_CORE_DIMM_A_SELECT __BIT(16)69 #define MCH_CORE_DIMM_A_DUAL_RANK __BIT(17)70 #define MCH_CORE_DIMM_B_DUAL_RANK __BIT(18)71 #define MCH_CORE_DIMM_A_X16 __BIT(19)72 #define MCH_CORE_DIMM_B_X16 __BIT(20)[all …]
57 #define PCI_E5V2_IMC_CPGC_MCMTR_CHN_DISABLE(c) __BIT(16 + (c))58 #define PCI_E5V3_IMC_CPGC_MCMTR_CHN_DISABLE(c) __BIT(18 + (c))59 #define PCI_E5V3_IMC_CPGC_MCMTR_DDR4 __BIT(14)62 #define PCI_E5_IMC_CPGC_MCMTR_ECC_EN __BIT(2)80 #define PCI_E5V3_IMC_CTAD_DIMMMTR_DDR4 __BIT(20)81 #define PCI_E5_IMC_CTAD_DIMMMTR_RANK_DISABLE(r) __BIT(16 + (r))83 #define PCI_E5_IMC_CTAD_DIMMMTR_DIMM_POP __BIT(14)137 #define PCI_E5_IMC_ERROR_COR_ERR_CNT_HI_OVFL __BIT(31)139 #define PCI_E5_IMC_ERROR_COR_ERR_CNT_LO_OVFL __BIT(15)184 #define PCI_E5_IMC_THERMAL_CHN_TEMP_CFG_OLTT_EN __BIT(31)[all …]
15 #define PCI_X3400UC_MC_CTRL_ECCEN __BIT(1)17 #define PCI_X3400UC_MC_STS_ECCEN __BIT(4)30 #define PCI_X3400UC_MCT2_COR_DIMM0_OV __BIT(15)32 #define PCI_X3400UC_MCT2_COR_DIMM1_OV __BIT(31)
68 #define __BIT(__n) (((__n) == 32) ? 0 : ((uint32_t)1 << (__n))) macro73 ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))
97 #undef __BIT98 #define __BIT(__n) __BIT64(__n) macro
1968 if (val & __BIT(7)) in sign_extend()1971 if (val & __BIT(15)) in sign_extend()1974 if (val & __BIT(31)) in sign_extend()