1 /* $FreeBSD: head/sys/dev/usb/controller/xhcireg.h 268354 2014-07-07 05:17:16Z hselasky $ */ 2 3 /*- 4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _XHCIREG_H_ 29 #define _XHCIREG_H_ 30 31 /* XHCI PCI config registers */ 32 #define PCI_XHCI_CBMEM 0x10 /* configuration base MEM */ 33 #define PCI_XHCI_USBREV 0x60 /* RO USB protocol revision */ 34 #define PCI_USB_REV_3_0 0x30 /* USB 3.0 */ 35 #define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ 36 37 #define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */ 38 #define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */ 39 #define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */ 40 #define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */ 41 42 /* XHCI capability registers */ 43 #define XHCI_CAPLENGTH 0x00 /* RO capability */ 44 #define XHCI_RESERVED 0x01 /* Reserved */ 45 #define XHCI_HCIVERSION 0x02 /* RO Interface version number */ 46 #define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ 47 #define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ 48 #define XHCI_HCSPARAMS1 0x04 /* RO structual parameters 1 */ 49 #define XHCI_HCS1_DEVSLOT_MAX(x)((x) & 0xFF) 50 #define XHCI_HCS1_IRQ_MAX(x) (((x) >> 8) & 0x3FF) 51 #define XHCI_HCS1_N_PORTS(x) (((x) >> 24) & 0xFF) 52 #define XHCI_HCSPARAMS2 0x08 /* RO structual parameters 2 */ 53 #define XHCI_HCS2_IST(x) ((x) & 0xF) 54 #define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xF) 55 #define XHCI_HCS2_SPR(x) (((x) >> 24) & 0x1) 56 #define XHCI_HCS2_SPB_MAX(x) (((x) >> 27) & 0x7F) 57 #define XHCI_HCSPARAMS3 0x0C /* RO structual parameters 3 */ 58 #define XHCI_HCS3_U1_DEL(x) ((x) & 0xFF) 59 #define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xFFFF) 60 #define XHCI_HCSPARAMS0 0x10 /* RO capability parameters */ 61 #define XHCI_HCS0_AC64(x) ((x) & 0x1) /* 64-bit capable */ 62 #define XHCI_HCS0_BNC(x) (((x) >> 1) & 0x1) /* BW negotiation */ 63 #define XHCI_HCS0_CSZ(x) (((x) >> 2) & 0x1) /* context size */ 64 #define XHCI_HCS0_PPC(x) (((x) >> 3) & 0x1) /* port power control */ 65 #define XHCI_HCS0_PIND(x) (((x) >> 4) & 0x1) /* port indicators */ 66 #define XHCI_HCS0_LHRC(x) (((x) >> 5) & 0x1) /* light HC reset */ 67 #define XHCI_HCS0_LTC(x) (((x) >> 6) & 0x1) /* latency tolerance msg */ 68 #define XHCI_HCS0_NSS(x) (((x) >> 7) & 0x1) /* no secondary sid */ 69 #define XHCI_HCS0_PSA_SZ_MAX(x) (((x) >> 12) & 0xF) /* max pri. stream array size */ 70 #define XHCI_HCS0_XECP(x) (((x) >> 16) & 0xFFFF) /* extended capabilities pointer */ 71 #define XHCI_DBOFF 0x14 /* RO doorbell offset */ 72 #define XHCI_RTSOFF 0x18 /* RO runtime register space offset */ 73 74 /* XHCI operational registers. Offset given by XHCI_CAPLENGTH register */ 75 #define XHCI_USBCMD 0x00 /* XHCI command */ 76 #define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */ 77 #define XHCI_CMD_HCRST 0x00000002 /* RW Host Controller Reset */ 78 #define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */ 79 #define XHCI_CMD_HSEE 0x00000008 /* RW Host System Error Enable */ 80 #define XHCI_CMD_LHCRST 0x00000080 /* RO/RW Light Host Controller Reset */ 81 #define XHCI_CMD_CSS 0x00000100 /* RW Controller Save State */ 82 #define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore State */ 83 #define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */ 84 #define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */ 85 #define XHCI_USBSTS 0x04 /* XHCI status */ 86 #define XHCI_STS_HCH 0x00000001 /* RO - Host Controller Halted */ 87 #define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */ 88 #define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */ 89 #define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */ 90 #define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */ 91 #define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */ 92 #define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */ 93 #define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */ 94 #define XHCI_STS_HCE 0x00001000 /* RO - Host Controller Error */ 95 #define XHCI_PAGESIZE 0x08 /* XHCI page size mask */ 96 #define XHCI_PAGESIZE_4K 0x00000001 /* 4K Page Size */ 97 #define XHCI_PAGESIZE_8K 0x00000002 /* 8K Page Size */ 98 #define XHCI_PAGESIZE_16K 0x00000004 /* 16K Page Size */ 99 #define XHCI_PAGESIZE_32K 0x00000008 /* 32K Page Size */ 100 #define XHCI_PAGESIZE_64K 0x00000010 /* 64K Page Size */ 101 #define XHCI_DNCTRL 0x14 /* XHCI device notification control */ 102 #define XHCI_DNCTRL_MASK(n) (1U << (n)) 103 #define XHCI_CRCR_LO 0x18 /* XHCI command ring control */ 104 #define XHCI_CRCR_LO_RCS 0x00000001 /* RW - consumer cycle state */ 105 #define XHCI_CRCR_LO_CS 0x00000002 /* RW - command stop */ 106 #define XHCI_CRCR_LO_CA 0x00000004 /* RW - command abort */ 107 #define XHCI_CRCR_LO_CRR 0x00000008 /* RW - command ring running */ 108 #define XHCI_CRCR_LO_MASK 0x0000000F 109 #define XHCI_CRCR_HI 0x1C /* XHCI command ring control */ 110 #define XHCI_DCBAAP_LO 0x30 /* XHCI dev context BA pointer */ 111 #define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */ 112 #define XHCI_CONFIG 0x38 113 #define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slots enabled */ 114 115 /* XHCI port status registers */ 116 #define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */ 117 #define XHCI_PS_CCS 0x00000001 /* RO - current connect status */ 118 #define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */ 119 #define XHCI_PS_OCA 0x00000008 /* RO - over current active */ 120 #define XHCI_PS_PR 0x00000010 /* RW - port reset */ 121 #define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */ 122 #define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */ 123 #define XHCI_PS_PP 0x00000200 /* RW - port power */ 124 #define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */ 125 #define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */ 126 #define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */ 127 #define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */ 128 #define XHCI_PS_CSC 0x00020000 /* RW - connect status change */ 129 #define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */ 130 #define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */ 131 #define XHCI_PS_OCC 0x00100000 /* RW - over-current change */ 132 #define XHCI_PS_PRC 0x00200000 /* RW - port reset change */ 133 #define XHCI_PS_PLC 0x00400000 /* RW - port link state change */ 134 #define XHCI_PS_CEC 0x00800000 /* RW - config error change */ 135 #define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */ 136 #define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */ 137 #define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */ 138 #define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */ 139 #define XHCI_PS_DR 0x40000000 /* RO - device removable */ 140 #define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */ 141 #define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */ 142 143 #define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) /* XHCI status and control */ 144 #define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */ 145 #define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */ 146 #define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */ 147 #define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */ 148 #define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */ 149 #define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */ 150 #define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */ 151 #define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) /* RW - host initiated resume duration */ 152 #define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) /* RW - host initiated resume duration */ 153 #define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */ 154 #define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */ 155 #define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */ 156 #define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* XHCI port link info */ 157 #define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errors */ 158 #define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */ 159 160 /* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */ 161 #define XHCI_MFINDEX 0x0000 /* RO - microframe index */ 162 #define XHCI_MFINDEX_GET(x) ((x) & 0x3FFF) 163 #define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* XHCI interrupt management */ 164 #define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */ 165 #define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */ 166 #define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */ 167 #define XHCI_IMOD_IVAL_GET(x) (((x) >> 0) & 0xFFFF) /* 250ns unit */ 168 #define XHCI_IMOD_IVAL_SET(x) (((x) & 0xFFFF) << 0) /* 250ns unit */ 169 #define XHCI_IMOD_ICNT_GET(x) (((x) >> 16) & 0xFFFF) /* 250ns unit */ 170 #define XHCI_IMOD_ICNT_SET(x) (((x) & 0xFFFF) << 16) /* 250ns unit */ 171 #define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQs/second */ 172 #define XHCI_IMOD_DEFAULT_LP 0x000003F8U /* 4000 IRQs/second - LynxPoint */ 173 #define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) /* XHCI event ring segment table size */ 174 #define XHCI_ERSTS_GET(x) ((x) & 0xFFFF) 175 #define XHCI_ERSTS_SET(x) ((x) & 0xFFFF) 176 #define XHCI_ERSTBA_LO(n) (0x0030 + (0x20 * (n))) /* XHCI event ring segment table BA */ 177 #define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) /* XHCI event ring segment table BA */ 178 #define XHCI_ERDP_LO(n) (0x0038 + (0x20 * (n))) /* XHCI event ring dequeue pointer */ 179 #define XHCI_ERDP_LO_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */ 180 #define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */ 181 #define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) /* XHCI event ring dequeue pointer */ 182 183 /* XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */ 184 #define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 185 #define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */ 186 #define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */ 187 #define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */ 188 #define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) /* RW - doorbell stream ID */ 189 190 /* XHCI legacy support */ 191 #define XHCI_XECP_ID(x) ((x) & 0xFF) 192 #define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xFF) 193 #define XHCI_XECP_BIOS_SEM 0x0002 194 #define XHCI_XECP_OS_SEM 0x0003 195 196 /* XHCI capability ID's */ 197 #define XHCI_ID_USB_LEGACY 0x0001 198 #define XHCI_ID_PROTOCOLS 0x0002 199 #define XHCI_ID_POWER_MGMT 0x0003 200 #define XHCI_ID_VIRTUALIZATION 0x0004 201 #define XHCI_ID_MSG_IRQ 0x0005 202 #define XHCI_ID_USB_LOCAL_MEM 0x0006 203 204 /* XHCI register R/W wrappers */ 205 #define XREAD1(sc, what, a) \ 206 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 207 (a) + (sc)->sc_##what##_off) 208 #define XREAD2(sc, what, a) \ 209 bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 210 (a) + (sc)->sc_##what##_off) 211 #define XREAD4(sc, what, a) \ 212 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 213 (a) + (sc)->sc_##what##_off) 214 #define XWRITE1(sc, what, a, x) \ 215 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 216 (a) + (sc)->sc_##what##_off, (x)) 217 #define XWRITE2(sc, what, a, x) \ 218 bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 219 (a) + (sc)->sc_##what##_off, (x)) 220 #define XWRITE4(sc, what, a, x) \ 221 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 222 (a) + (sc)->sc_##what##_off, (x)) 223 224 #endif /* _XHCIREG_H_ */ 225