1 /* 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/vge/if_vgevar.h,v 1.4 2005/06/10 16:49:16 brooks Exp $ 33 * $DragonFly: src/sys/dev/netif/vge/if_vgevar.h,v 1.1 2006/05/20 07:15:17 sephe Exp $ 34 */ 35 36 #if !defined(__i386__) 37 #define VGE_FIXUP_RX 38 #endif 39 40 #define VGE_JUMBO_MTU 9000 41 42 #define VGE_IFQ_MAXLEN 64 43 44 #define VGE_TX_DESC_CNT 256 45 #define VGE_RX_DESC_CNT 256 /* Must be a multiple of 4!! */ 46 #define VGE_RING_ALIGN 256 47 #define VGE_RX_LIST_SZ (VGE_RX_DESC_CNT * sizeof(struct vge_rx_desc)) 48 #define VGE_TX_LIST_SZ (VGE_TX_DESC_CNT * sizeof(struct vge_tx_desc)) 49 #define VGE_TX_DESC_INC(x) (x = (x + 1) % VGE_TX_DESC_CNT) 50 #define VGE_RX_DESC_INC(x) (x = (x + 1) % VGE_RX_DESC_CNT) 51 #define VGE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 52 #define VGE_ADDR_HI(y) ((uint64_t) (y) >> 32) 53 #define VGE_BUFLEN(y) ((y) & 0x7FFF) 54 #define VGE_OWN(x) (le32toh((x)->vge_sts) & VGE_RDSTS_OWN) 55 #define VGE_RXBYTES(x) ((le32toh((x)->vge_sts) & \ 56 VGE_RDSTS_BUFSIZ) >> 16) 57 #define VGE_MIN_FRAMELEN 60 58 59 #ifdef VGE_FIXUP_RX 60 #define VGE_ETHER_ALIGN sizeof(uint32_t) 61 #else 62 #define VGE_ETHER_ALIGN 0 63 #endif 64 65 struct vge_type { 66 uint16_t vge_vid; 67 uint16_t vge_did; 68 char *vge_name; 69 }; 70 71 struct vge_softc; 72 73 struct vge_dmaload_arg { 74 struct vge_softc *sc; 75 int vge_idx; 76 int vge_maxsegs; 77 struct mbuf *vge_m0; 78 uint32_t vge_flags; 79 }; 80 81 struct vge_list_data { 82 struct mbuf *vge_tx_mbuf[VGE_TX_DESC_CNT]; 83 struct mbuf *vge_rx_mbuf[VGE_RX_DESC_CNT]; 84 int vge_tx_prodidx; 85 int vge_rx_prodidx; 86 int vge_tx_considx; 87 int vge_tx_free; 88 bus_dmamap_t vge_tx_dmamap[VGE_TX_DESC_CNT]; 89 bus_dmamap_t vge_rx_dmamap[VGE_RX_DESC_CNT]; 90 bus_dma_tag_t vge_mtag; /* mbuf mapping tag */ 91 bus_dma_tag_t vge_rx_list_tag; 92 bus_dmamap_t vge_rx_list_map; 93 struct vge_rx_desc *vge_rx_list; 94 bus_addr_t vge_rx_list_addr; 95 bus_dma_tag_t vge_tx_list_tag; 96 bus_dmamap_t vge_tx_list_map; 97 struct vge_tx_desc *vge_tx_list; 98 bus_addr_t vge_tx_list_addr; 99 }; 100 101 struct vge_softc { 102 struct arpcom arpcom; 103 bus_space_handle_t vge_bhandle; /* bus space handle */ 104 bus_space_tag_t vge_btag; /* bus space tag */ 105 int vge_res_rid; 106 int vge_irq_rid; 107 struct resource *vge_res; 108 struct resource *vge_irq; 109 void *vge_intrhand; 110 device_t vge_miibus; 111 bus_dma_tag_t vge_parent_tag; 112 bus_dma_tag_t vge_tag; 113 uint8_t vge_type; 114 int vge_if_flags; 115 int vge_rx_consumed; 116 int vge_link; 117 int vge_camidx; 118 struct mbuf *vge_head; 119 struct mbuf *vge_tail; 120 121 struct ifpoll_compat vge_npoll; 122 struct vge_list_data vge_ldata; 123 124 int suspended; /* 0 = normal 1 = suspended */ 125 }; 126 127 #define VGE_LOCK(_sc) mtx_lock(&(_sc)->vge_mtx) 128 #define VGE_UNLOCK(_sc) mtx_unlock(&(_sc)->vge_mtx) 129 #define VGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vge_mtx, MA_OWNED) 130 131 /* 132 * register space access macros 133 */ 134 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 135 bus_space_write_stream_4(sc->vge_btag, sc->vge_bhandle, reg, val) 136 #define CSR_WRITE_4(sc, reg, val) \ 137 bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val) 138 #define CSR_WRITE_2(sc, reg, val) \ 139 bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val) 140 #define CSR_WRITE_1(sc, reg, val) \ 141 bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val) 142 143 #define CSR_READ_4(sc, reg) \ 144 bus_space_read_4(sc->vge_btag, sc->vge_bhandle, reg) 145 #define CSR_READ_2(sc, reg) \ 146 bus_space_read_2(sc->vge_btag, sc->vge_bhandle, reg) 147 #define CSR_READ_1(sc, reg) \ 148 bus_space_read_1(sc->vge_btag, sc->vge_bhandle, reg) 149 150 #define CSR_SETBIT_1(sc, reg, x) \ 151 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 152 #define CSR_SETBIT_2(sc, reg, x) \ 153 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 154 #define CSR_SETBIT_4(sc, reg, x) \ 155 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 156 157 #define CSR_CLRBIT_1(sc, reg, x) \ 158 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 159 #define CSR_CLRBIT_2(sc, reg, x) \ 160 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 161 #define CSR_CLRBIT_4(sc, reg, x) \ 162 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 163 164 #define VGE_TIMEOUT 10000 165