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Searched refs:VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h9481 #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L macro
HDdce_8_0_sh_mask.h11095 #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 macro
HDdce_10_0_sh_mask.h11479 #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 macro
HDdce_11_0_sh_mask.h11291 #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 macro
HDdce_11_2_sh_mask.h12545 #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 macro
HDdce_12_0_sh_mask.h2119 #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h1669 #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK … macro