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Searched refs:VCE_UENC_REG_CLOCK_GATING (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDvce_v2_0.c51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
53 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
67 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
69 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
93 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
96 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
164 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_resume()
HDvce_v1_0.c117 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
119 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
130 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
132 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
153 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_init_cg()
155 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_init_cg()
225 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v1_0_resume()
HDsid.h1907 #define VCE_UENC_REG_CLOCK_GATING 0x205c0 macro
HDcikd.h2132 #define VCE_UENC_REG_CLOCK_GATING 0x207c0 macro