Home
last modified time | relevance | path

Searched refs:UPLL_CTLREQ_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDradeon_uvd.c1028 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); in radeon_uvd_send_upll_ctlreq()
1033 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); in radeon_uvd_send_upll_ctlreq()
1044 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); in radeon_uvd_send_upll_ctlreq()
HDrv770d.h46 # define UPLL_CTLREQ_MASK 0x00000008 macro
HDsid.h131 # define UPLL_CTLREQ_MASK 0x00000008 macro
HDsi.c7459 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
7464 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
7475 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
HDevergreend.h352 # define UPLL_CTLREQ_MASK 0x00000008 macro
HDr600d.h1560 # define UPLL_CTLREQ_MASK 0x00000008 macro
HDr600.c205 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); in r600_set_uvd_clocks()