1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_stereg.h,v 1.5.2.3 2002/08/21 15:26:01 ambrisko Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_stereg.h,v 1.7 2006/08/01 18:10:05 swildner Exp $ 34 */ 35 36 /* 37 * Register definitions for the Sundance Technologies ST201 PCI 38 * fast ethernet controller. The register space is 128 bytes long and 39 * can be accessed using either PCI I/O space or PCI memory mapping. 40 * There are 32-bit, 16-bit and 8-bit registers. 41 */ 42 43 #define STE_DMACTL 0x00 44 #define STE_TX_DMALIST_PTR 0x04 45 #define STE_TX_DMABURST_THRESH 0x08 46 #define STE_TX_DMAURG_THRESH 0x09 47 #define STE_TX_DMAPOLL_PERIOD 0x0A 48 #define STE_RX_DMASTATUS 0x0C 49 #define STE_RX_DMALIST_PTR 0x10 50 #define STE_RX_DMABURST_THRESH 0x14 51 #define STE_RX_DMAURG_THRESH 0x15 52 #define STE_RX_DMAPOLL_PERIOD 0x16 53 #define STE_DEBUGCTL 0x1A 54 #define STE_ASICCTL 0x30 55 #define STE_EEPROM_DATA 0x34 56 #define STE_EEPROM_CTL 0x36 57 #define STE_FIFOCTL 0x3A 58 #define STE_TX_STARTTHRESH 0x3C 59 #define STE_RX_EARLYTHRESH 0x3E 60 #define STE_EXT_ROMADDR 0x40 61 #define STE_EXT_ROMDATA 0x44 62 #define STE_WAKE_EVENT 0x45 63 #define STE_TX_STATUS 0x46 64 #define STE_TX_FRAMEID 0x47 65 #define STE_COUNTDOWN 0x48 66 #define STE_ISR_ACK 0x4A 67 #define STE_IMR 0x4C 68 #define STE_ISR 0x4E 69 #define STE_MACCTL0 0x50 70 #define STE_MACCTL1 0x52 71 #define STE_PAR0 0x54 72 #define STE_PAR1 0x56 73 #define STE_PAR2 0x58 74 #define STE_MAX_FRAMELEN 0x5A 75 #define STE_RX_MODE 0x5C 76 #define STE_TX_RECLAIM_THRESH 0x5D 77 #define STE_PHYCTL 0x5E 78 #define STE_MAR0 0x60 79 #define STE_MAR1 0x62 80 #define STE_MAR2 0x64 81 #define STE_MAR3 0x66 82 #define STE_STATS 0x68 83 84 #define STE_LATE_COLLS 0x75 85 #define STE_MULTI_COLLS 0x76 86 #define STE_SINGLE_COLLS 0x77 87 88 #define STE_DMACTL_RXDMA_STOPPED 0x00000001 89 #define STE_DMACTL_TXDMA_CMPREQ 0x00000002 90 #define STE_DMACTL_TXDMA_STOPPED 0x00000004 91 #define STE_DMACTL_RXDMA_COMPLETE 0x00000008 92 #define STE_DMACTL_TXDMA_COMPLETE 0x00000010 93 #define STE_DMACTL_RXDMA_STALL 0x00000100 94 #define STE_DMACTL_RXDMA_UNSTALL 0x00000200 95 #define STE_DMACTL_TXDMA_STALL 0x00000400 96 #define STE_DMACTL_TXDMA_UNSTALL 0x00000800 97 #define STE_DMACTL_TXDMA_INPROG 0x00004000 98 #define STE_DMACTL_DMA_HALTINPROG 0x00008000 99 #define STE_DMACTL_RXEARLY_ENABLE 0x00020000 100 #define STE_DMACTL_COUNTDOWN_SPEED 0x00040000 101 #define STE_DMACTL_COUNTDOWN_MODE 0x00080000 102 #define STE_DMACTL_MWI_DISABLE 0x00100000 103 #define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000 104 #define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000 105 #define STE_DMACTL_TARGET_ABORT 0x40000000 106 #define STE_DMACTL_MASTER_ABORT 0x80000000 107 108 /* 109 * TX DMA burst thresh is the number of 32-byte blocks that 110 * must be loaded into the TX Fifo before a TXDMA burst request 111 * will be issued. 112 */ 113 #define STE_TXDMABURST_THRESH 0x1F 114 115 /* 116 * The number of 32-byte blocks in the TX FIFO falls below the 117 * TX DMA urgent threshold, a TX DMA urgent request will be 118 * generated. 119 */ 120 #define STE_TXDMAURG_THRESH 0x3F 121 122 /* 123 * Number of 320ns intervals between polls of the TXDMA next 124 * descriptor pointer (if we're using polling mode). 125 */ 126 #define STE_TXDMA_POLL_PERIOD 0x7F 127 128 #define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF 129 #define STE_RX_DMASTATUS_RXERR 0x00004000 130 #define STE_RX_DMASTATUS_DMADONE 0x00008000 131 #define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000 132 #define STE_RX_DMASTATUS_RUNT 0x00020000 133 #define STE_RX_DMASTATUS_ALIGNERR 0x00040000 134 #define STE_RX_DMASTATUS_CRCERR 0x00080000 135 #define STE_RX_DMASTATUS_GIANT 0x00100000 136 #define STE_RX_DMASTATUS_DRIBBLE 0x00800000 137 #define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000 138 139 /* 140 * RX DMA burst thresh is the number of 32-byte blocks that 141 * must be present in the RX FIFO before a RXDMA bus master 142 * request will be issued. 143 */ 144 #define STE_RXDMABURST_THRESH 0xFF 145 146 /* 147 * The number of 32-byte blocks in the RX FIFO falls below the 148 * RX DMA urgent threshold, a RX DMA urgent request will be 149 * generated. 150 */ 151 #define STE_RXDMAURG_THRESH 0x1F 152 153 /* 154 * Number of 320ns intervals between polls of the RXDMA complete 155 * bit in the status field on the current RX descriptor (if we're 156 * using polling mode). 157 */ 158 #define STE_RXDMA_POLL_PERIOD 0x7F 159 160 #define STE_DEBUGCTL_GPIO0_CTL 0x0001 161 #define STE_DEBUGCTL_GPIO1_CTL 0x0002 162 #define STE_DEBUGCTL_GPIO0_DATA 0x0004 163 #define STE_DEBUGCTL_GPIO1_DATA 0x0008 164 165 #define STE_ASICCTL_ROMSIZE 0x00000002 166 #define STE_ASICCTL_TX_LARGEPKTS 0x00000004 167 #define STE_ASICCTL_RX_LARGEPKTS 0x00000008 168 #define STE_ASICCTL_EXTROM_DISABLE 0x00000010 169 #define STE_ASICCTL_PHYSPEED_10 0x00000020 170 #define STE_ASICCTL_PHYSPEED_100 0x00000040 171 #define STE_ASICCTL_PHYMEDIA 0x00000080 172 #define STE_ASICCTL_FORCEDCONFIG 0x00000700 173 #define STE_ASICCTL_D3RESET_DISABLE 0x00000800 174 #define STE_ASICCTL_SPEEDUPMODE 0x00002000 175 #define STE_ASICCTL_LEDMODE 0x00004000 176 #define STE_ASICCTL_RSTOUT_POLARITY 0x00008000 177 #define STE_ASICCTL_GLOBAL_RESET 0x00010000 178 #define STE_ASICCTL_RX_RESET 0x00020000 179 #define STE_ASICCTL_TX_RESET 0x00040000 180 #define STE_ASICCTL_DMA_RESET 0x00080000 181 #define STE_ASICCTL_FIFO_RESET 0x00100000 182 #define STE_ASICCTL_NETWORK_RESET 0x00200000 183 #define STE_ASICCTL_HOST_RESET 0x00400000 184 #define STE_ASICCTL_AUTOINIT_RESET 0x00800000 185 #define STE_ASICCTL_EXTRESET_RESET 0x01000000 186 #define STE_ASICCTL_SOFTINTR 0x02000000 187 #define STE_ASICCTL_RESET_BUSY 0x04000000 188 189 #define STE_ASICCTL1_GLOBAL_RESET 0x0001 190 #define STE_ASICCTL1_RX_RESET 0x0002 191 #define STE_ASICCTL1_TX_RESET 0x0004 192 #define STE_ASICCTL1_DMA_RESET 0x0008 193 #define STE_ASICCTL1_FIFO_RESET 0x0010 194 #define STE_ASICCTL1_NETWORK_RESET 0x0020 195 #define STE_ASICCTL1_HOST_RESET 0x0040 196 #define STE_ASICCTL1_AUTOINIT_RESET 0x0080 197 #define STE_ASICCTL1_EXTRESET_RESET 0x0100 198 #define STE_ASICCTL1_SOFTINTR 0x0200 199 #define STE_ASICCTL1_RESET_BUSY 0x0400 200 201 #define STE_EECTL_ADDR 0x00FF 202 #define STE_EECTL_OPCODE 0x0300 203 #define STE_EECTL_BUSY 0x1000 204 205 #define STE_EEOPCODE_WRITE 0x0100 206 #define STE_EEOPCODE_READ 0x0200 207 #define STE_EEOPCODE_ERASE 0x0300 208 209 #define STE_FIFOCTL_RAMTESTMODE 0x0001 210 #define STE_FIFOCTL_OVERRUNMODE 0x0200 211 #define STE_FIFOCTL_RXFIFOFULL 0x0800 212 #define STE_FIFOCTL_TX_BUSY 0x4000 213 #define STE_FIFOCTL_RX_BUSY 0x8000 214 215 /* 216 * The number of bytes that must in present in the TX FIFO before 217 * transmission begins. Value should be in increments of 4 bytes. 218 */ 219 #define STE_TXSTART_THRESH 0x1FFC 220 221 /* 222 * Number of bytes that must be present in the RX FIFO before 223 * an RX EARLY interrupt is generated. 224 */ 225 #define STE_RXEARLY_THRESH 0x1FFC 226 227 #define STE_WAKEEVENT_WAKEPKT_ENB 0x01 228 #define STE_WAKEEVENT_MAGICPKT_ENB 0x02 229 #define STE_WAKEEVENT_LINKEVT_ENB 0x04 230 #define STE_WAKEEVENT_WAKEPOLARITY 0x08 231 #define STE_WAKEEVENT_WAKEPKTEVENT 0x10 232 #define STE_WAKEEVENT_MAGICPKTEVENT 0x20 233 #define STE_WAKEEVENT_LINKEVENT 0x40 234 #define STE_WAKEEVENT_WAKEONLAN_ENB 0x80 235 236 #define STE_TXSTATUS_RECLAIMERR 0x02 237 #define STE_TXSTATUS_STATSOFLOW 0x04 238 #define STE_TXSTATUS_EXCESSCOLLS 0x08 239 #define STE_TXSTATUS_UNDERRUN 0x10 240 #define STE_TXSTATUS_TXINTR_REQ 0x40 241 #define STE_TXSTATUS_TXDONE 0x80 242 243 #define STE_ISRACK_INTLATCH 0x0001 244 #define STE_ISRACK_HOSTERR 0x0002 245 #define STE_ISRACK_TX_DONE 0x0004 246 #define STE_ISRACK_MACCTL_FRAME 0x0008 247 #define STE_ISRACK_RX_DONE 0x0010 248 #define STE_ISRACK_RX_EARLY 0x0020 249 #define STE_ISRACK_SOFTINTR 0x0040 250 #define STE_ISRACK_STATS_OFLOW 0x0080 251 #define STE_ISRACK_LINKEVENT 0x0100 252 #define STE_ISRACK_TX_DMADONE 0x0200 253 #define STE_ISRACK_RX_DMADONE 0x0400 254 255 #define STE_IMR_HOSTERR 0x0002 256 #define STE_IMR_TX_DONE 0x0004 257 #define STE_IMR_MACCTL_FRAME 0x0008 258 #define STE_IMR_RX_DONE 0x0010 259 #define STE_IMR_RX_EARLY 0x0020 260 #define STE_IMR_SOFTINTR 0x0040 261 #define STE_IMR_STATS_OFLOW 0x0080 262 #define STE_IMR_LINKEVENT 0x0100 263 #define STE_IMR_TX_DMADONE 0x0200 264 #define STE_IMR_RX_DMADONE 0x0400 265 266 #define STE_INTRS \ 267 (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \ 268 STE_IMR_TX_DONE|STE_IMR_HOSTERR| \ 269 STE_IMR_LINKEVENT) 270 271 #define STE_ISR_INTLATCH 0x0001 272 #define STE_ISR_HOSTERR 0x0002 273 #define STE_ISR_TX_DONE 0x0004 274 #define STE_ISR_MACCTL_FRAME 0x0008 275 #define STE_ISR_RX_DONE 0x0010 276 #define STE_ISR_RX_EARLY 0x0020 277 #define STE_ISR_SOFTINTR 0x0040 278 #define STE_ISR_STATS_OFLOW 0x0080 279 #define STE_ISR_LINKEVENT 0x0100 280 #define STE_ISR_TX_DMADONE 0x0200 281 #define STE_ISR_RX_DMADONE 0x0400 282 283 /* 284 * Note: the Sundance manual gives the impression that the's 285 * only one 32-bit MACCTL register. In fact, there are two 286 * 16-bit registers side by side, and you have to access them 287 * separately. 288 */ 289 #define STE_MACCTL0_IPG 0x0003 290 #define STE_MACCTL0_FULLDUPLEX 0x0020 291 #define STE_MACCTL0_RX_GIANTS 0x0040 292 #define STE_MACCTL0_FLOWCTL_ENABLE 0x0100 293 #define STE_MACCTL0_RX_FCS 0x0200 294 #define STE_MACCTL0_FIFOLOOPBK 0x0400 295 #define STE_MACCTL0_MACLOOPBK 0x0800 296 297 #define STE_MACCTL1_COLLDETECT 0x0001 298 #define STE_MACCTL1_CARRSENSE 0x0002 299 #define STE_MACCTL1_TX_BUSY 0x0004 300 #define STE_MACCTL1_TX_ERROR 0x0008 301 #define STE_MACCTL1_STATS_ENABLE 0x0020 302 #define STE_MACCTL1_STATS_DISABLE 0x0040 303 #define STE_MACCTL1_STATS_ENABLED 0x0080 304 #define STE_MACCTL1_TX_ENABLE 0x0100 305 #define STE_MACCTL1_TX_DISABLE 0x0200 306 #define STE_MACCTL1_TX_ENABLED 0x0400 307 #define STE_MACCTL1_RX_ENABLE 0x0800 308 #define STE_MACCTL1_RX_DISABLE 0x1000 309 #define STE_MACCTL1_RX_ENABLED 0x2000 310 #define STE_MACCTL1_PAUSED 0x4000 311 312 #define STE_IPG_96BT 0x00000000 313 #define STE_IPG_128BT 0x00000001 314 #define STE_IPG_224BT 0x00000002 315 #define STE_IPG_544BT 0x00000003 316 317 #define STE_RXMODE_UNICAST 0x01 318 #define STE_RXMODE_ALLMULTI 0x02 319 #define STE_RXMODE_BROADCAST 0x04 320 #define STE_RXMODE_PROMISC 0x08 321 #define STE_RXMODE_MULTIHASH 0x10 322 #define STE_RXMODE_ALLIPMULTI 0x20 323 324 #define STE_PHYCTL_MCLK 0x01 325 #define STE_PHYCTL_MDATA 0x02 326 #define STE_PHYCTL_MDIR 0x04 327 #define STE_PHYCTL_CLK25_DISABLE 0x08 328 #define STE_PHYCTL_DUPLEXPOLARITY 0x10 329 #define STE_PHYCTL_DUPLEXSTAT 0x20 330 #define STE_PHYCTL_SPEEDSTAT 0x40 331 #define STE_PHYCTL_LINKSTAT 0x80 332 333 /* 334 * EEPROM offsets. 335 */ 336 #define STE_EEADDR_CONFIGPARM 0x00 337 #define STE_EEADDR_ASICCTL 0x02 338 #define STE_EEADDR_SUBSYS_ID 0x04 339 #define STE_EEADDR_SUBVEN_ID 0x08 340 341 #define STE_EEADDR_NODE0 0x10 342 #define STE_EEADDR_NODE1 0x12 343 #define STE_EEADDR_NODE2 0x14 344 345 /* PCI registers */ 346 #define STE_PCI_VENDOR_ID 0x00 347 #define STE_PCI_DEVICE_ID 0x02 348 #define STE_PCI_COMMAND 0x04 349 #define STE_PCI_STATUS 0x06 350 #define STE_PCI_CLASSCODE 0x09 351 #define STE_PCI_LATENCY_TIMER 0x0D 352 #define STE_PCI_HEADER_TYPE 0x0E 353 #define STE_PCI_LOIO 0x10 354 #define STE_PCI_LOMEM 0x14 355 #define STE_PCI_BIOSROM 0x30 356 #define STE_PCI_INTLINE 0x3C 357 #define STE_PCI_INTPIN 0x3D 358 #define STE_PCI_MINGNT 0x3E 359 #define STE_PCI_MINLAT 0x0F 360 361 #define STE_PCI_CAPID 0x50 /* 8 bits */ 362 #define STE_PCI_NEXTPTR 0x51 /* 8 bits */ 363 #define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 364 #define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 365 366 #define STE_PME_EN 0x0010 367 #define STE_PME_STATUS 0x8000 368 369 370 struct ste_stats { 371 u_int32_t ste_rx_bytes; 372 u_int32_t ste_tx_bytes; 373 u_int16_t ste_tx_frames; 374 u_int16_t ste_rx_frames; 375 u_int8_t ste_carrsense_errs; 376 u_int8_t ste_late_colls; 377 u_int8_t ste_multi_colls; 378 u_int8_t ste_single_colls; 379 u_int8_t ste_tx_frames_defered; 380 u_int8_t ste_rx_lost_frames; 381 u_int8_t ste_tx_excess_defers; 382 u_int8_t ste_tx_abort_excess_colls; 383 u_int8_t ste_tx_bcast_frames; 384 u_int8_t ste_rx_bcast_frames; 385 u_int8_t ste_tx_mcast_frames; 386 u_int8_t ste_rx_mcast_frames; 387 }; 388 389 struct ste_frag { 390 u_int32_t ste_addr; 391 u_int32_t ste_len; 392 }; 393 394 #define STE_FRAG_LAST 0x80000000 395 #define STE_FRAG_LEN 0x00001FFF 396 397 #define STE_MAXFRAGS 8 398 399 struct ste_desc { 400 u_int32_t ste_next; 401 u_int32_t ste_ctl; 402 struct ste_frag ste_frags[STE_MAXFRAGS]; 403 }; 404 405 struct ste_desc_onefrag { 406 u_int32_t ste_next; 407 u_int32_t ste_status; 408 struct ste_frag ste_frag; 409 }; 410 411 #define STE_TXCTL_WORDALIGN 0x00000003 412 #define STE_TXCTL_FRAMEID 0x000003FC 413 #define STE_TXCTL_NOCRC 0x00002000 414 #define STE_TXCTL_TXINTR 0x00008000 415 #define STE_TXCTL_DMADONE 0x00010000 416 #define STE_TXCTL_DMAINTR 0x80000000 417 418 #define STE_RXSTAT_FRAMELEN 0x00001FFF 419 #define STE_RXSTAT_FRAME_ERR 0x00004000 420 #define STE_RXSTAT_DMADONE 0x00008000 421 #define STE_RXSTAT_FIFO_OFLOW 0x00010000 422 #define STE_RXSTAT_RUNT 0x00020000 423 #define STE_RXSTAT_ALIGNERR 0x00040000 424 #define STE_RXSTAT_CRCERR 0x00080000 425 #define STE_RXSTAT_GIANT 0x00100000 426 #define STE_RXSTAT_DRIBBLEBITS 0x00800000 427 #define STE_RXSTAT_DMA_OFLOW 0x01000000 428 #define STE_RXATAT_ONEBUF 0x10000000 429 430 /* 431 * register space access macros 432 */ 433 #define CSR_WRITE_4(sc, reg, val) \ 434 bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val) 435 #define CSR_WRITE_2(sc, reg, val) \ 436 bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val) 437 #define CSR_WRITE_1(sc, reg, val) \ 438 bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val) 439 440 #define CSR_READ_4(sc, reg) \ 441 bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg) 442 #define CSR_READ_2(sc, reg) \ 443 bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg) 444 #define CSR_READ_1(sc, reg) \ 445 bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg) 446 447 #define STE_TIMEOUT 1000 448 #define STE_MIN_FRAMELEN 60 449 #define STE_PACKET_SIZE 1536 450 #define ETHER_ALIGN 2 451 #define STE_RX_LIST_CNT 64 452 #define STE_TX_LIST_CNT 64 453 #define STE_INC(x, y) (x) = (x + 1) % y 454 #define STE_NEXT(x, y) (x + 1) % y 455 456 struct ste_type { 457 u_int16_t ste_vid; 458 u_int16_t ste_did; 459 char *ste_name; 460 }; 461 462 struct ste_list_data { 463 struct ste_desc_onefrag ste_rx_list[STE_RX_LIST_CNT]; 464 struct ste_desc ste_tx_list[STE_TX_LIST_CNT]; 465 u_int8_t ste_pad[STE_MIN_FRAMELEN]; 466 }; 467 468 struct ste_chain { 469 struct ste_desc *ste_ptr; 470 struct mbuf *ste_mbuf; 471 struct ste_chain *ste_next; 472 struct ste_chain *ste_prev; 473 u_int32_t ste_phys; 474 }; 475 476 struct ste_chain_onefrag { 477 struct ste_desc_onefrag *ste_ptr; 478 struct mbuf *ste_mbuf; 479 struct ste_chain_onefrag *ste_next; 480 }; 481 482 struct ste_chain_data { 483 struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; 484 struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; 485 struct ste_chain_onefrag *ste_rx_head; 486 487 int ste_tx_prod; 488 int ste_tx_cons; 489 int ste_tx_cnt; 490 }; 491 492 struct ste_softc { 493 struct arpcom arpcom; 494 bus_space_tag_t ste_btag; 495 bus_space_handle_t ste_bhandle; 496 struct resource *ste_res; 497 struct resource *ste_irq; 498 void *ste_intrhand; 499 struct ste_type *ste_info; 500 device_t ste_miibus; 501 device_t ste_dev; 502 int ste_tx_thresh; 503 u_int8_t ste_link; 504 int ste_if_flags; 505 int ste_tx_prev_idx; 506 struct ste_list_data *ste_ldata; 507 struct ste_chain_data ste_cdata; 508 struct callout ste_stat_timer; 509 u_int8_t ste_one_phy; 510 }; 511 512 struct ste_mii_frame { 513 u_int8_t mii_stdelim; 514 u_int8_t mii_opcode; 515 u_int8_t mii_phyaddr; 516 u_int8_t mii_regaddr; 517 u_int8_t mii_turnaround; 518 u_int16_t mii_data; 519 }; 520 521 /* 522 * MII constants 523 */ 524 #define STE_MII_STARTDELIM 0x01 525 #define STE_MII_READOP 0x02 526 #define STE_MII_WRITEOP 0x01 527 #define STE_MII_TURNAROUND 0x02 528