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Searched refs:STEP_0_SPLL_POST_DIV (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDr600_dpm.c483 STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK); in r600_engine_clock_entry_set_post_divider()
HDr600d.h1363 # define STEP_0_SPLL_POST_DIV(x) ((x) << 0) macro