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Searched refs:SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_8_0_sh_mask.h1485 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 macro
HDdce_10_0_sh_mask.h1515 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 macro
HDdce_11_0_sh_mask.h1423 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 macro
HDdce_11_2_sh_mask.h1551 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 macro
HDdce_12_0_sh_mask.h2609 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_sh_mask.h3608 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … macro