1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sfreg.h,v 1.6.2.1 2001/08/16 20:35:04 wpaul Exp $ 33 */ 34 35 /* 36 * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K 37 * register space. These registers can be accessed in the following way: 38 * - PCI config registers are always accessible through PCI config space 39 * - Full 512K space mapped into memory using PCI memory mapped access 40 * - 256-byte I/O space mapped through PCI I/O access 41 * - Full 512K space mapped through indirect I/O using PCI I/O access 42 * It's possible to use either memory mapped mode or I/O mode to access 43 * the registers, but memory mapped is usually the easiest. All registers 44 * are 32 bits wide and must be accessed using 32-bit operations. 45 */ 46 47 /* 48 * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify 49 * the exact kind of NIC on which the ASIC is mounted. Currently there 50 * are six different variations. Note: the Adaptec manual lists code 0x28 51 * for two different NICs: the 62044 and the 69011/TX. This is a typo: 52 * the code for the 62044 is really 0x18. 53 * 54 * Note that there also appears to be an 0x19 code for a newer rev 55 * 62044 card. 56 */ 57 #define AD_SUBSYSID_62011_REV0 0x0008 /* single port 10/100baseTX 64-bit */ 58 #define AD_SUBSYSID_62011_REV1 0x0009 /* single port 10/100baseTX 64-bit */ 59 #define AD_SUBSYSID_62022 0x0010 /* dual port 10/100baseTX 64-bit */ 60 #define AD_SUBSYSID_62044_REV0 0x0018 /* quad port 10/100baseTX 64-bit */ 61 #define AD_SUBSYSID_62044_REV1 0x0019 /* quad port 10/100baseTX 64-bit */ 62 #define AD_SUBSYSID_62020 0x0020 /* single port 10/100baseFX 64-bit */ 63 #define AD_SUBSYSID_69011 0x0028 /* single port 10/100baseTX 32-bit */ 64 65 /* 66 * Starfire internal register space map. The entire register space 67 * is available using PCI memory mapped mode. The SF_RMAP_INTREG 68 * space is available using PCI I/O mode. The entire space can be 69 * accessed using indirect I/O using the indirect I/O addr and 70 * indirect I/O data registers located within the SF_RMAP_INTREG space. 71 */ 72 #define SF_RMAP_ROMADDR_BASE 0x00000 /* Expansion ROM space */ 73 #define SF_RMAP_ROMADDR_MAX 0x3FFFF 74 75 #define SF_RMAP_EXGPIO_BASE 0x40000 /* External general purpose regs */ 76 #define SF_RMAP_EXGPIO_MAX 0x3FFFF 77 78 #define SF_RMAP_INTREG_BASE 0x50000 /* Internal functional registers */ 79 #define SF_RMAP_INTREG_MAX 0x500FF 80 #define SF_RMAP_GENREG_BASE 0x50100 /* General purpose registers */ 81 #define SF_RMAP_GENREG_MAX 0x5FFFF 82 83 #define SF_RMAP_FIFO_BASE 0x60000 84 #define SF_RMAP_FIFO_MAX 0x6FFFF 85 86 #define SF_RMAP_STS_BASE 0x70000 87 #define SF_RMAP_STS_MAX 0x70083 88 89 #define SF_RMAP_RSVD_BASE 0x70084 90 #define SF_RMAP_RSVD_MAX 0x7FFFF 91 92 /* 93 * PCI config header registers, 0x0000 to 0x003F 94 */ 95 #define SF_PCI_VENDOR_ID 0x0000 96 #define SF_PCI_DEVICE_ID 0x0002 97 #define SF_PCI_COMMAND 0x0004 98 #define SF_PCI_STATUS 0x0006 99 #define SF_PCI_REVID 0x0008 100 #define SF_PCI_CLASSCODE 0x0009 101 #define SF_PCI_CACHELEN 0x000C 102 #define SF_PCI_LATENCY_TIMER 0x000D 103 #define SF_PCI_HEADER_TYPE 0x000E 104 #define SF_PCI_LOMEM 0x0010 105 #define SF_PCI_LOIO 0x0014 106 #define SF_PCI_SUBVEN_ID 0x002C 107 #define SF_PCI_SYBSYS_ID 0x002E 108 #define SF_PCI_BIOSROM 0x0030 109 #define SF_PCI_INTLINE 0x003C 110 #define SF_PCI_INTPIN 0x003D 111 #define SF_PCI_MINGNT 0x003E 112 #define SF_PCI_MINLAT 0x003F 113 114 /* 115 * PCI registers, 0x0040 to 0x006F 116 */ 117 #define SF_PCI_DEVCFG 0x0040 118 #define SF_BACCTL 0x0044 119 #define SF_PCI_MON1 0x0048 120 #define SF_PCI_MON2 0x004C 121 #define SF_PCI_CAPID 0x0050 /* 8 bits */ 122 #define SF_PCI_NEXTPTR 0x0051 /* 8 bits */ 123 #define SF_PCI_PWRMGMTCAP 0x0052 /* 16 bits */ 124 #define SF_PCI_PWRMGMTCTRL 0x0054 /* 16 bits */ 125 #define SF_PCI_PME_EVENT 0x0058 126 #define SF_PCI_EECTL 0x0060 127 #define SF_PCI_COMPLIANCE 0x0064 128 #define SF_INDIRECTIO_ADDR 0x0068 129 #define SF_INDIRECTIO_DATA 0x006C 130 131 #define SF_PCIDEVCFG_RESET 0x00000001 132 #define SF_PCIDEVCFG_FORCE64 0x00000002 133 #define SF_PCIDEVCFG_SYSTEM64 0x00000004 134 #define SF_PCIDEVCFG_RSVD0 0x00000008 135 #define SF_PCIDEVCFG_INCR_INB 0x00000010 136 #define SF_PCIDEVCFG_ABTONPERR 0x00000020 137 #define SF_PCIDEVCFG_STPONPERR 0x00000040 138 #define SF_PCIDEVCFG_MR_ENB 0x00000080 139 #define SF_PCIDEVCFG_FIFOTHR 0x00000F00 140 #define SF_PCIDEVCFG_STPONCA 0x00001000 141 #define SF_PCIDEVCFG_PCIMEN 0x00002000 /* enable PCI bus master */ 142 #define SF_PCIDEVCFG_LATSTP 0x00004000 143 #define SF_PCIDEVCFG_BYTE_ENB 0x00008000 144 #define SF_PCIDEVCFG_EECSWIDTH 0x00070000 145 #define SF_PCIDEVCFG_STPMWCA 0x00080000 146 #define SF_PCIDEVCFG_REGCSWIDTH 0x00700000 147 #define SF_PCIDEVCFG_INTR_ENB 0x00800000 148 #define SF_PCIDEVCFG_DPR_ENB 0x01000000 149 #define SF_PCIDEVCFG_RSVD1 0x02000000 150 #define SF_PCIDEVCFG_RSVD2 0x04000000 151 #define SF_PCIDEVCFG_STA_ENB 0x08000000 152 #define SF_PCIDEVCFG_RTA_ENB 0x10000000 153 #define SF_PCIDEVCFG_RMA_ENB 0x20000000 154 #define SF_PCIDEVCFG_SSE_ENB 0x40000000 155 #define SF_PCIDEVCFG_DPE_ENB 0x80000000 156 157 #define SF_BACCTL_BACDMA_ENB 0x00000001 158 #define SF_BACCTL_PREFER_RXDMA 0x00000002 159 #define SF_BACCTL_PREFER_TXDMA 0x00000004 160 #define SF_BACCTL_SINGLE_DMA 0x00000008 161 #define SF_BACCTL_SWAPMODE_DATA 0x00000030 162 #define SF_BACCTL_SWAPMODE_DESC 0x000000C0 163 164 #define SF_SWAPMODE_LE 0x00000000 165 #define SF_SWAPMODE_BE 0x00000010 166 167 #define SF_PSTATE_MASK 0x0003 168 #define SF_PSTATE_D0 0x0000 169 #define SF_PSTATE_D1 0x0001 170 #define SF_PSTATE_D2 0x0002 171 #define SF_PSTATE_D3 0x0003 172 #define SF_PME_EN 0x0010 173 #define SF_PME_STATUS 0x8000 174 175 176 /* 177 * Ethernet registers 0x0070 to 0x00FF 178 */ 179 #define SF_GEN_ETH_CTL 0x0070 180 #define SF_TIMER_CTL 0x0074 181 #define SF_CURTIME 0x0078 182 #define SF_ISR 0x0080 183 #define SF_ISR_SHADOW 0x0084 184 #define SF_IMR 0x0088 185 #define SF_GPIO 0x008C 186 #define SF_TXDQ_CTL 0x0090 187 #define SF_TXDQ_ADDR_HIPRIO 0x0094 188 #define SF_TXDQ_ADDR_LOPRIO 0x0098 189 #define SF_TXDQ_ADDR_HIADDR 0x009C 190 #define SF_TXDQ_PRODIDX 0x00A0 191 #define SF_TXDQ_CONSIDX 0x00A4 192 #define SF_TXDMA_STS1 0x00A8 193 #define SF_TXDMA_STS2 0x00AC 194 #define SF_TX_FRAMCTL 0x00B0 195 #define SF_TXCQ_ADDR_HI 0x00B4 196 #define SF_TXCQ_CTL 0x00B8 197 #define SF_RXCQ_CTL_1 0x00BC 198 #define SF_RXCQ_CTL_2 0x00C0 199 #define SF_CQ_CONSIDX 0x00C4 200 #define SF_CQ_PRODIDX 0x00C8 201 #define SF_CQ_RXQ2 0x00CC 202 #define SF_RXDMA_CTL 0x00D0 203 #define SF_RXDQ_CTL_1 0x00D4 204 #define SF_RXDQ_CTL_2 0x00D8 205 #define SF_RXDQ_ADDR_HIADDR 0x00DC 206 #define SF_RXDQ_ADDR_Q1 0x00E0 207 #define SF_RXDQ_ADDR_Q2 0x00E4 208 #define SF_RXDQ_PTR_Q1 0x00E8 209 #define SF_RXDQ_PTR_Q2 0x00EC 210 #define SF_RXDMA_STS 0x00F0 211 #define SF_RXFILT 0x00F4 212 #define SF_RX_FRAMETEST_OUT 0x00F8 213 214 /* Ethernet control register */ 215 #define SF_ETHCTL_RX_ENB 0x00000001 216 #define SF_ETHCTL_TX_ENB 0x00000002 217 #define SF_ETHCTL_RXDMA_ENB 0x00000004 218 #define SF_ETHCTL_TXDMA_ENB 0x00000008 219 #define SF_ETHCTL_RXGFP_ENB 0x00000010 220 #define SF_ETHCTL_TXGFP_ENB 0x00000020 221 #define SF_ETHCTL_SOFTINTR 0x00000800 222 223 /* Timer control register */ 224 #define SF_TIMER_IMASK_INTERVAL 0x0000001F 225 #define SF_TIMER_IMASK_MODE 0x00000060 226 #define SF_TIMER_SMALLFRAME_BYP 0x00000100 227 #define SF_TIMER_SMALLRX_FRAME 0x00000600 228 #define SF_TIMER_TIMES_TEN 0x00000800 229 #define SF_TIMER_RXHIPRIO_BYP 0x00001000 230 #define SF_TIMER_TX_DMADONE_DLY 0x00002000 231 #define SF_TIMER_TX_QDONE_DLY 0x00004000 232 #define SF_TIMER_TX_FRDONE_DLY 0x00008000 233 #define SF_TIMER_GENTIMER 0x00FF0000 234 #define SF_TIMER_ONESHOT 0x01000000 235 #define SF_TIMER_GENTIMER_RES 0x02000000 236 #define SF_TIMER_TIMEST_RES 0x04000000 237 #define SF_TIMER_RXQ2DONE_DLY 0x10000000 238 #define SF_TIMER_EARLYRX2_DLY 0x20000000 239 #define SF_TIMER_RXQ1DONE_DLY 0x40000000 240 #define SF_TIMER_EARLYRX1_DLY 0x80000000 241 242 /* Interrupt status register */ 243 #define SF_ISR_PCIINT_ASSERTED 0x00000001 244 #define SF_ISR_GFP_TX 0x00000002 245 #define SF_ISR_GFP_RX 0x00000004 246 #define SF_ISR_TX_BADID_HIPRIO 0x00000008 247 #define SF_ISR_TX_BADID_LOPRIO 0x00000010 248 #define SF_ISR_NO_TX_CSUM 0x00000020 249 #define SF_ISR_RXDQ2_NOBUFS 0x00000040 250 #define SF_ISR_RXGFP_NORESP 0x00000080 251 #define SF_ISR_RXDQ1_DMADONE 0x00000100 252 #define SF_ISR_RXDQ2_DMADONE 0x00000200 253 #define SF_ISR_RXDQ1_EARLY 0x00000400 254 #define SF_ISR_RXDQ2_EARLY 0x00000800 255 #define SF_ISR_TX_QUEUEDONE 0x00001000 256 #define SF_ISR_TX_DMADONE 0x00002000 257 #define SF_ISR_TX_TXDONE 0x00004000 258 #define SF_ISR_NORMALINTR 0x00008000 259 #define SF_ISR_RXDQ1_NOBUFS 0x00010000 260 #define SF_ISR_RXCQ2_NOBUFS 0x00020000 261 #define SF_ISR_TX_LOFIFO 0x00040000 262 #define SF_ISR_DMAERR 0x00080000 263 #define SF_ISR_PCIINT 0x00100000 264 #define SF_ISR_TXCQ_NOBUFS 0x00200000 265 #define SF_ISR_RXCQ1_NOBUFS 0x00400000 266 #define SF_ISR_SOFTINTR 0x00800000 267 #define SF_ISR_GENTIMER 0x01000000 268 #define SF_ISR_ABNORMALINTR 0x02000000 269 #define SF_ISR_RSVD0 0x04000000 270 #define SF_ISR_STATSOFLOW 0x08000000 271 #define SF_ISR_GPIO 0xF0000000 272 273 /* 274 * Shadow interrupt status register. Unlike the normal IRQ register, 275 * reading bits here does not automatically cause them to reset. 276 */ 277 #define SF_SISR_PCIINT_ASSERTED 0x00000001 278 #define SF_SISR_GFP_TX 0x00000002 279 #define SF_SISR_GFP_RX 0x00000004 280 #define SF_SISR_TX_BADID_HIPRIO 0x00000008 281 #define SF_SISR_TX_BADID_LOPRIO 0x00000010 282 #define SF_SISR_NO_TX_CSUM 0x00000020 283 #define SF_SISR_RXDQ2_NOBUFS 0x00000040 284 #define SF_SISR_RXGFP_NORESP 0x00000080 285 #define SF_SISR_RXDQ1_DMADONE 0x00000100 286 #define SF_SISR_RXDQ2_DMADONE 0x00000200 287 #define SF_SISR_RXDQ1_EARLY 0x00000400 288 #define SF_SISR_RXDQ2_EARLY 0x00000800 289 #define SF_SISR_TX_QUEUEDONE 0x00001000 290 #define SF_SISR_TX_DMADONE 0x00002000 291 #define SF_SISR_TX_TXDONE 0x00004000 292 #define SF_SISR_NORMALINTR 0x00008000 293 #define SF_SISR_RXDQ1_NOBUFS 0x00010000 294 #define SF_SISR_RXCQ2_NOBUFS 0x00020000 295 #define SF_SISR_TX_LOFIFO 0x00040000 296 #define SF_SISR_DMAERR 0x00080000 297 #define SF_SISR_PCIINT 0x00100000 298 #define SF_SISR_TXCQ_NOBUFS 0x00200000 299 #define SF_SISR_RXCQ1_NOBUFS 0x00400000 300 #define SF_SISR_SOFTINTR 0x00800000 301 #define SF_SISR_GENTIMER 0x01000000 302 #define SF_SISR_ABNORMALINTR 0x02000000 303 #define SF_SISR_RSVD0 0x04000000 304 #define SF_SISR_STATSOFLOW 0x08000000 305 #define SF_SISR_GPIO 0xF0000000 306 307 /* Interrupt mask register */ 308 #define SF_IMR_PCIINT_ASSERTED 0x00000001 309 #define SF_IMR_GFP_TX 0x00000002 310 #define SF_IMR_GFP_RX 0x00000004 311 #define SF_IMR_TX_BADID_HIPRIO 0x00000008 312 #define SF_IMR_TX_BADID_LOPRIO 0x00000010 313 #define SF_IMR_NO_TX_CSUM 0x00000020 314 #define SF_IMR_RXDQ2_NOBUFS 0x00000040 315 #define SF_IMR_RXGFP_NORESP 0x00000080 316 #define SF_IMR_RXDQ1_DMADONE 0x00000100 317 #define SF_IMR_RXDQ2_DMADONE 0x00000200 318 #define SF_IMR_RXDQ1_EARLY 0x00000400 319 #define SF_IMR_RXDQ2_EARLY 0x00000800 320 #define SF_IMR_TX_QUEUEDONE 0x00001000 321 #define SF_IMR_TX_DMADONE 0x00002000 322 #define SF_IMR_TX_TXDONE 0x00004000 323 #define SF_IMR_NORMALINTR 0x00008000 324 #define SF_IMR_RXDQ1_NOBUFS 0x00010000 325 #define SF_IMR_RXCQ2_NOBUFS 0x00020000 326 #define SF_IMR_TX_LOFIFO 0x00040000 327 #define SF_IMR_DMAERR 0x00080000 328 #define SF_IMR_PCIINT 0x00100000 329 #define SF_IMR_TXCQ_NOBUFS 0x00200000 330 #define SF_IMR_RXCQ1_NOBUFS 0x00400000 331 #define SF_IMR_SOFTINTR 0x00800000 332 #define SF_IMR_GENTIMER 0x01000000 333 #define SF_IMR_ABNORMALINTR 0x02000000 334 #define SF_IMR_RSVD0 0x04000000 335 #define SF_IMR_STATSOFLOW 0x08000000 336 #define SF_IMR_GPIO 0xF0000000 337 338 #define SF_INTRS \ 339 (SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE| \ 340 SF_IMR_TX_TXDONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE| \ 341 SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS| \ 342 SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW| \ 343 SF_IMR_TX_LOFIFO) 344 345 /* TX descriptor queue control registers */ 346 #define SF_TXDQCTL_DESCTYPE 0x00000007 347 #define SF_TXDQCTL_NODMACMP 0x00000008 348 #define SF_TXDQCTL_MINSPACE 0x00000070 349 #define SF_TXDQCTL_64BITADDR 0x00000080 350 #define SF_TXDQCTL_BURSTLEN 0x00003F00 351 #define SF_TXDQCTL_SKIPLEN 0x001F0000 352 #define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000 353 354 #define SF_TXBUFDESC_TYPE0 0x00000000 355 #define SF_TXBUFDESC_TYPE1 0x00000001 356 #define SF_TXBUFDESC_TYPE2 0x00000002 357 #define SF_TXBUFDESC_TYPE3 0x00000003 358 #define SF_TXBUFDESC_TYPE4 0x00000004 359 360 #define SF_TXMINSPACE_UNLIMIT 0x00000000 361 #define SF_TXMINSPACE_32BYTES 0x00000010 362 #define SF_TXMINSPACE_64BYTES 0x00000020 363 #define SF_TXMINSPACE_128BYTES 0x00000030 364 #define SF_TXMINSPACE_256BYTES 0x00000040 365 366 #define SF_TXSKIPLEN_0BYTES 0x00000000 367 #define SF_TXSKIPLEN_8BYTES 0x00010000 368 #define SF_TXSKIPLEN_16BYTES 0x00020000 369 #define SF_TXSKIPLEN_24BYTES 0x00030000 370 #define SF_TXSKIPLEN_32BYTES 0x00040000 371 372 /* TX frame control register */ 373 #define SF_TXFRMCTL_TXTHRESH 0x000000FF 374 #define SF_TXFRMCTL_CPLAFTERTX 0x00000100 375 #define SF_TXFRMCRL_DEBUG 0x0000FE00 376 #define SF_TXFRMCTL_STATUS 0x01FF0000 377 #define SF_TXFRMCTL_MAC_TXIF 0xFE000000 378 379 /* TX completion queue control register */ 380 #define SF_TXCQ_THRESH 0x0000000F 381 #define SF_TXCQ_COMMON 0x00000010 382 #define SF_TXCQ_SIZE 0x00000020 383 #define SF_TXCQ_WRITEENB 0x00000040 384 #define SF_TXCQ_USE_64BIT 0x00000080 385 #define SF_TXCQ_ADDR 0xFFFFFF00 386 387 /* RX completion queue control register */ 388 #define SF_RXCQ_THRESH 0x0000000F 389 #define SF_RXCQ_TYPE 0x00000030 390 #define SF_RXCQ_WRITEENB 0x00000040 391 #define SF_RXCQ_USE_64BIT 0x00000080 392 #define SF_RXCQ_ADDR 0xFFFFFF00 393 394 #define SF_RXCQTYPE_0 0x00000000 395 #define SF_RXCQTYPE_1 0x00000010 396 #define SF_RXCQTYPE_2 0x00000020 397 #define SF_RXCQTYPE_3 0x00000030 398 399 /* TX descriptor queue producer index register */ 400 #define SF_TXDQ_PRODIDX_LOPRIO 0x000007FF 401 #define SF_TXDQ_PRODIDX_HIPRIO 0x07FF0000 402 403 /* TX descriptor queue consumer index register */ 404 #define SF_TXDQ_CONSIDX_LOPRIO 0x000007FF 405 #define SF_TXDQ_CONSIDX_HIPRIO 0x07FF0000 406 407 /* Completion queue consumer index register */ 408 #define SF_CQ_CONSIDX_RXQ1 0x000003FF 409 #define SF_CQ_CONSIDX_RXTHRMODE 0x00008000 410 #define SF_CQ_CONSIDX_TXQ 0x03FF0000 411 #define SF_CQ_CONSIDX_TXTHRMODE 0x80000000 412 413 /* Completion queue producer index register */ 414 #define SF_CQ_PRODIDX_RXQ1 0x000003FF 415 #define SF_CQ_PRODIDX_TXQ 0x03FF0000 416 417 /* RX completion queue 2 consumer/producer index register */ 418 #define SF_CQ_RXQ2_CONSIDX 0x000003FF 419 #define SF_CQ_RXQ2_RXTHRMODE 0x00008000 420 #define SF_CQ_RXQ2_PRODIDX 0x03FF0000 421 422 #define SF_CQ_RXTHRMODE_INT_ON 0x00008000 423 #define SF_CQ_RXTHRMODE_INT_OFF 0x00000000 424 #define SF_CQ_TXTHRMODE_INT_ON 0x80000000 425 #define SF_CQ_TXTHRMODE_INT_OFF 0x00000000 426 427 #define SF_IDX_LO(x) ((x) & 0x000007FF) 428 #define SF_IDX_HI(x) (((x) >> 16) & 0x000007FF) 429 430 /* RX DMA control register */ 431 #define SF_RXDMA_BURSTSIZE 0x0000007F 432 #define SF_RXDMA_FPTESTMODE 0x00000080 433 #define SF_RXDMA_HIPRIOTHRESH 0x00000F00 434 #define SF_RXDMA_RXEARLYTHRESH 0x0001F000 435 #define SF_RXDMA_DMACRC 0x00040000 436 #define SF_RXDMA_USEBKUPQUEUE 0x00080000 437 #define SF_RXDMA_QUEUEMODE 0x00700000 438 #define SF_RXDMA_RXCQ2_ON 0x00800000 439 #define SF_RXDMA_CSUMMODE 0x03000000 440 #define SF_RXDMA_DMAPAUSEPKTS 0x04000000 441 #define SF_RXDMA_DMACTLPKTS 0x08000000 442 #define SF_RXDMA_DMACRXERRPKTS 0x10000000 443 #define SF_RXDMA_DMABADPKTS 0x20000000 444 #define SF_RXDMA_DMARUNTS 0x40000000 445 #define SF_RXDMA_REPORTBADPKTS 0x80000000 446 447 #define SF_RXDQMODE_Q1ONLY 0x00100000 448 #define SF_RXDQMODE_Q2_ON_FP 0x00200000 449 #define SF_RXDQMODE_Q2_ON_SHORT 0x00300000 450 #define SF_RXDQMODE_Q2_ON_PRIO 0x00400000 451 #define SF_RXDQMODE_SPLITHDR 0x00500000 452 453 #define SF_RXCSUMMODE_IGNORE 0x00000000 454 #define SF_RXCSUMMODE_REJECT_BAD_TCP 0x01000000 455 #define SF_RXCSUMMODE_REJECT_BAD_TCPUDP 0x02000000 456 #define SF_RXCSUMMODE_RSVD 0x03000000 457 458 /* RX descriptor queue control registers */ 459 #define SF_RXDQCTL_MINDESCTHR 0x0000007F 460 #define SF_RXDQCTL_Q1_WE 0x00000080 461 #define SF_RXDQCTL_DESCSPACE 0x00000700 462 #define SF_RXDQCTL_64BITDADDR 0x00000800 463 #define SF_RXDQCTL_64BITBADDR 0x00001000 464 #define SF_RXDQCTL_VARIABLE 0x00002000 465 #define SF_RXDQCTL_ENTRIES 0x00004000 466 #define SF_RXDQCTL_PREFETCH 0x00008000 467 #define SF_RXDQCTL_BUFLEN 0xFFFF0000 468 469 #define SF_DESCSPACE_4BYTES 0x00000000 470 #define SF_DESCSPACE_8BYTES 0x00000100 471 #define SF_DESCSPACE_16BYTES 0x00000200 472 #define SF_DESCSPACE_32BYTES 0x00000300 473 #define SF_DESCSPACE_64BYTES 0x00000400 474 #define SF_DESCSPACE_128_BYTES 0x00000500 475 476 /* RX buffer consumer/producer index registers */ 477 #define SF_RXDQ_PRODIDX 0x000007FF 478 #define SF_RXDQ_CONSIDX 0x07FF0000 479 480 /* RX filter control register */ 481 #define SF_RXFILT_PROMISC 0x00000001 482 #define SF_RXFILT_ALLMULTI 0x00000002 483 #define SF_RXFILT_BROAD 0x00000004 484 #define SF_RXFILT_HASHPRIO 0x00000008 485 #define SF_RXFILT_HASHMODE 0x00000030 486 #define SF_RXFILT_PERFMODE 0x000000C0 487 #define SF_RXFILT_VLANMODE 0x00000300 488 #define SF_RXFILT_WAKEMODE 0x00000C00 489 #define SF_RXFILT_MULTI_NOBROAD 0x00001000 490 #define SF_RXFILT_MIN_VLANPRIO 0x0000E000 491 #define SF_RXFILT_PEFECTPRIO 0xFFFF0000 492 493 /* Hash filtering mode */ 494 #define SF_HASHMODE_OFF 0x00000000 495 #define SF_HASHMODE_WITHVLAN 0x00000010 496 #define SF_HASHMODE_ANYVLAN 0x00000020 497 #define SF_HASHMODE_ANY 0x00000030 498 499 /* Perfect filtering mode */ 500 #define SF_PERFMODE_OFF 0x00000000 501 #define SF_PERFMODE_NORMAL 0x00000040 502 #define SF_PERFMODE_INVERSE 0x00000080 503 #define SF_PERFMODE_VLAN 0x000000C0 504 505 /* VLAN mode */ 506 #define SF_VLANMODE_OFF 0x00000000 507 #define SF_VLANMODE_NOSTRIP 0x00000100 508 #define SF_VLANMODE_STRIP 0x00000200 509 #define SF_VLANMODE_RSVD 0x00000300 510 511 /* Wakeup mode */ 512 #define SF_WAKEMODE_OFF 0x00000000 513 #define SF_WAKEMODE_FILTER 0x00000400 514 #define SF_WAKEMODE_FP 0x00000800 515 #define SF_WAKEMODE_HIPRIO 0x00000C00 516 517 /* 518 * Extra PCI registers 0x0100 to 0x0FFF 519 */ 520 #define SF_PCI_TARGSTAT 0x0100 521 #define SF_PCI_MASTSTAT1 0x0104 522 #define SF_PCI_MASTSTAT2 0x0108 523 #define SF_PCI_DMAHOSTADDR_LO 0x010C 524 #define SF_BAC_DMADIAG0 0x0110 525 #define SF_BAC_DMADIAG1 0x0114 526 #define SF_BAC_DMADIAG2 0x0118 527 #define SF_BAC_DMADIAG3 0x011C 528 #define SF_PAR0 0x0120 529 #define SF_PAR1 0x0124 530 #define SF_PCICB_FUNCEVENT 0x0130 531 #define SF_PCICB_FUNCEVENT_MASK 0x0134 532 #define SF_PCICB_FUNCSTATE 0x0138 533 #define SF_PCICB_FUNCFORCE 0x013C 534 535 /* 536 * Serial EEPROM registers 0x1000 to 0x1FFF 537 * Presumeably the EEPROM is mapped into this 8K window. 538 */ 539 #define SF_EEADDR_BASE 0x1000 540 #define SF_EEADDR_MAX 0x1FFF 541 542 #define SF_EE_NODEADDR 14 543 544 /* 545 * MII registers registers 0x2000 to 0x3FFF 546 * There are 32 sets of 32 registers, one set for each possible 547 * PHY address. Each 32 bit register is split into a 16-bit data 548 * port and a couple of status bits. 549 */ 550 551 #define SF_MIIADDR_BASE 0x2000 552 #define SF_MIIADDR_MAX 0x3FFF 553 #define SF_MII_BLOCKS 32 554 555 #define SF_MII_DATAVALID 0x80000000 556 #define SF_MII_BUSY 0x40000000 557 #define SF_MII_DATAPORT 0x0000FFFF 558 559 #define SF_PHY_REG(phy, reg) \ 560 (SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) + \ 561 (reg * sizeof(u_int32_t))) 562 563 /* 564 * Ethernet extra registers 0x4000 to 0x4FFF 565 */ 566 #define SF_TESTMODE 0x4000 567 #define SF_RX_FRAMEPROC_CTL 0x4004 568 #define SF_TX_FRAMEPROC_CTL 0x4008 569 570 /* 571 * MAC registers 0x5000 to 0x5FFF 572 */ 573 #define SF_MACCFG_1 0x5000 574 #define SF_MACCFG_2 0x5004 575 #define SF_BKTOBKIPG 0x5008 576 #define SF_NONBKTOBKIPG 0x500C 577 #define SF_COLRETRY 0x5010 578 #define SF_MAXLEN 0x5014 579 #define SF_TXNIBBLECNT 0x5018 580 #define SF_TXBYTECNT 0x501C 581 #define SF_RETXCNT 0x5020 582 #define SF_RANDNUM 0x5024 583 #define SF_RANDNUM_MASK 0x5028 584 #define SF_TOTALTXCNT 0x5034 585 #define SF_RXBYTECNT 0x5040 586 #define SF_TXPAUSETIMER 0x5060 587 #define SF_VLANTYPE 0x5064 588 #define SF_MIISTATUS 0x5070 589 590 #define SF_MACCFG1_HUGEFRAMES 0x00000001 591 #define SF_MACCFG1_FULLDUPLEX 0x00000002 592 #define SF_MACCFG1_AUTOPAD 0x00000004 593 #define SF_MACCFG1_HDJAM 0x00000008 594 #define SF_MACCFG1_DELAYCRC 0x00000010 595 #define SF_MACCFG1_NOBACKOFF 0x00000020 596 #define SF_MACCFG1_LENGTHCHECK 0x00000040 597 #define SF_MACCFG1_PUREPREAMBLE 0x00000080 598 #define SF_MACCFG1_PASSALLRX 0x00000100 599 #define SF_MACCFG1_PREAM_DETCNT 0x00000200 600 #define SF_MACCFG1_RX_FLOWENB 0x00000400 601 #define SF_MACCFG1_TX_FLOWENB 0x00000800 602 #define SF_MACCFG1_TESTMODE 0x00003000 603 #define SF_MACCFG1_MIILOOPBK 0x00004000 604 #define SF_MACCFG1_SOFTRESET 0x00008000 605 606 /* 607 * There are the recommended IPG nibble counter settings 608 * specified in the Adaptec manual for full duplex and 609 * half duplex operation. 610 */ 611 #define SF_IPGT_FDX 0x15 612 #define SF_IPGT_HDX 0x11 613 614 /* 615 * RX filter registers 0x6000 to 0x6FFF 616 */ 617 #define SF_RXFILT_PERFECT_BASE 0x6000 618 #define SF_RXFILT_PERFECT_MAX 0x60FF 619 #define SF_RXFILT_PERFECT_SKIP 0x0010 620 #define SF_RXFILT_PERFECT_CNT 0x0010 621 622 #define SF_RXFILT_HASH_BASE 0x6100 623 #define SF_RXFILT_HASH_MAX 0x62FF 624 #define SF_RXFILT_HASH_SKIP 0x0010 625 #define SF_RXFILT_HASH_CNT 0x001F 626 #define SF_RXFILT_HASH_ADDROFF 0x0000 627 #define SF_RXFILT_HASH_PRIOOFF 0x0004 628 #define SF_RXFILT_HASH_VLANOFF 0x0008 629 630 /* 631 * Statistics registers 0x7000 to 0x7FFF 632 */ 633 #define SF_STATS_BASE 0x7000 634 #define SF_STATS_END 0x7FFF 635 636 /* 637 * TX frame processor instruction space 0x8000 to 0x9FFF 638 */ 639 640 /* 641 * RX frame processor instruction space 0xA000 to 0xBFFF 642 */ 643 644 /* 645 * Ethernet FIFO access space 0xC000 to 0xDFFF 646 */ 647 648 /* 649 * Reserved 0xE000 to 0xFFFF 650 */ 651 652 /* 653 * Descriptor data structures. 654 */ 655 656 657 /* Receive descriptor formats. */ 658 #define SF_RX_MINSPACING 8 659 #define SF_RX_DLIST_CNT 256 660 #define SF_RX_CLIST_CNT 1024 661 #define SF_RX_HOSTADDR(x) (((x) >> 2) & 0x3FFFFFFF) 662 663 /* 664 * RX buffer descriptor type 0, 32-bit addressing. Note that we 665 * program the RX buffer queue control register(s) to allow a 666 * descriptor spacing of 16 bytes, which leaves room after each 667 * descriptor to store a pointer to the mbuf for each buffer. 668 */ 669 struct sf_rx_bufdesc_type0 { 670 u_int32_t sf_valid:1, 671 sf_end:1, 672 sf_addrlo:30; 673 u_int32_t sf_pad0; 674 #ifndef __LP64__ 675 u_int32_t sf_pad1; 676 #endif 677 struct mbuf *sf_mbuf; 678 }; 679 680 /* 681 * RX buffer descriptor type 0, 64-bit addressing. 682 */ 683 struct sf_rx_bufdesc_type1 { 684 u_int32_t sf_valid:1, 685 sf_end:1, 686 sf_addrlo:30; 687 u_int32_t sf_addrhi; 688 #ifndef __LP64__ 689 u_int32_t sf_pad; 690 #endif 691 struct mbuf *sf_mbuf; 692 }; 693 694 /* 695 * RX completion descriptor, type 0 (short). 696 */ 697 struct sf_rx_cmpdesc_type0 { 698 u_int32_t sf_len:16, 699 sf_endidx:11, 700 sf_status1:3, 701 sf_id:2; 702 }; 703 704 /* 705 * RX completion descriptor, type 1 (basic). Includes vlan ID 706 * if this is a vlan-addressed packet, plus extended status. 707 */ 708 struct sf_rx_cmpdesc_type1 { 709 u_int32_t sf_len:16, 710 sf_endidx:11, 711 sf_status1:3, 712 sf_id:2; 713 u_int16_t sf_status2; 714 u_int16_t sf_vlanid; 715 }; 716 717 /* 718 * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP 719 * checksum instead of vlan tag, plus extended status. 720 */ 721 struct sf_rx_cmpdesc_type2 { 722 u_int32_t sf_len:16, 723 sf_endidx:11, 724 sf_status1:3, 725 sf_id:2; 726 u_int16_t sf_status2; 727 u_int16_t sf_cksum; 728 }; 729 730 /* 731 * RX completion descriptor type 3 (full). Includes timestamp, partial 732 * TCP/IP checksum, vlan tag plus priority, two extended status fields. 733 */ 734 struct sf_rx_cmpdesc_type3 { 735 u_int32_t sf_len:16, 736 sf_endidx:11, 737 sf_status1:3, 738 sf_id:2; 739 u_int32_t sf_startidx:10, 740 sf_status3:6, 741 sf_status2:16; 742 u_int16_t sf_cksum; 743 u_int16_t sf_vlanid_prio; 744 u_int32_t sf_timestamp; 745 }; 746 747 #define SF_RXSTAT1_QUEUE 0x1 748 #define SF_RXSTAT1_FIFOFULL 0x2 749 #define SF_RXSTAT1_OK 0x4 750 751 /* 0=unknown,5=unsupported */ 752 #define SF_RXSTAT2_FRAMETYPE 0x0007 /* 1=IPv4,2=IPv2,3=IPX,4=ICMP */ 753 #define SF_RXSTAT2_UDP 0x0008 754 #define SF_RXSTAT2_TCP 0x0010 755 #define SF_RXSTAT2_FRAG 0x0020 756 #define SF_RXSTAT2_PCSUM_OK 0x0040 /* partial checksum ok */ 757 #define SF_RXSTAT2_CSUM_BAD 0x0080 /* TCP/IP checksum bad */ 758 #define SF_RXSTAT2_CSUM_OK 0x0100 /* TCP/IP checksum ok */ 759 #define SF_RXSTAT2_VLAN 0x0200 760 #define SF_RXSTAT2_BADRXCODE 0x0400 761 #define SF_RXSTAT2_DRIBBLE 0x0800 762 #define SF_RXSTAT2_ISL_CRCERR 0x1000 763 #define SF_RXSTAT2_CRCERR 0x2000 764 #define SF_RXSTAT2_HASH 0x4000 765 #define SF_RXSTAT2_PERFECT 0x8000 766 767 #define SF_RXSTAT3_TRAILER 0x01 768 #define SF_RXSTAT3_HEADER 0x02 769 #define SF_RXSTAT3_CONTROL 0x04 770 #define SF_RXSTAT3_PAUSE 0x08 771 #define SF_RXSTAT3_ISL 0x10 772 773 /* 774 * Transmit descriptor formats. 775 * Each transmit descriptor type allows for a skip field at the 776 * start of each structure. The size of the skip field can vary, 777 * however we always set it for 8 bytes, which is enough to hold 778 * a pointer (32 bits on x86, 64-bits on alpha) that we can use 779 * to hold the address of the head of the mbuf chain for the 780 * frame or fragment associated with the descriptor. This saves 781 * us from having to create a separate pointer array to hold 782 * the mbuf addresses. 783 */ 784 #define SF_TX_BUFDESC_ID 0xB 785 #define SF_MAXFRAGS 14 786 #define SF_TX_MINSPACING 128 787 #define SF_TX_DLIST_CNT 128 788 #define SF_TX_DLIST_SIZE 16384 789 #define SF_TX_SKIPLEN 1 790 #define SF_TX_CLIST_CNT 1024 791 792 struct sf_frag { 793 u_int32_t sf_addr; 794 u_int16_t sf_fraglen; 795 u_int16_t sf_pktlen; 796 }; 797 798 struct sf_frag_msdos { 799 u_int16_t sf_pktlen; 800 u_int16_t sf_fraglen; 801 u_int32_t sf_addr; 802 }; 803 804 /* 805 * TX frame descriptor type 0, 32-bit addressing. One descriptor can 806 * be used to map multiple packet fragments. We use this format since 807 * BSD networking fragments packet data across mbuf chains. Note that 808 * the number of fragments can be variable depending on how the descriptor 809 * spacing is specified in the TX descriptor queue control register. 810 * We always use a spacing of 128 bytes, and a skipfield length of 8 811 * bytes: this means 16 bytes for the descriptor, including the skipfield, 812 * with 121 bytes left for fragment maps. Each fragment requires 8 bytes, 813 * which allows for 14 fragments per descriptor. The total size of the 814 * transmit buffer queue is limited to 16384 bytes, so with a spacing of 815 * 128 bytes per descriptor, we have room for 128 descriptors in the queue. 816 */ 817 struct sf_tx_bufdesc_type0 { 818 #ifndef __LP64__ 819 u_int32_t sf_pad; 820 #endif 821 struct mbuf *sf_mbuf; 822 u_int32_t sf_rsvd0:24, 823 sf_crcen:1, 824 sf_caltcp:1, 825 sf_end:1, 826 sf_intr:1, 827 sf_id:4; 828 u_int8_t sf_fragcnt; 829 u_int8_t sf_rsvd2; 830 u_int16_t sf_rsvd1; 831 struct sf_frag sf_frags[SF_MAXFRAGS]; 832 }; 833 834 /* 835 * TX buffer descriptor type 1, 32-bit addressing. Each descriptor 836 * maps a single fragment. 837 */ 838 struct sf_tx_bufdesc_type1 { 839 #ifndef __LP64__ 840 u_int32_t sf_pad; 841 #endif 842 struct mbuf *sf_mbuf; 843 u_int32_t sf_fraglen:16, 844 sf_fragcnt:8, 845 sf_crcen:1, 846 sf_caltcp:1, 847 sf_end:1, 848 sf_intr:1, 849 sf_id:4; 850 u_int32_t sf_addr; 851 }; 852 853 /* 854 * TX buffer descriptor type 2, 64-bit addressing. Each descriptor 855 * maps a single fragment. 856 */ 857 struct sf_tx_bufdesc_type2 { 858 #ifndef __LP64__ 859 u_int32_t sf_pad; 860 #endif 861 struct mbuf *sf_mbuf; 862 u_int32_t sf_fraglen:16, 863 sf_fragcnt:8, 864 sf_crcen:1, 865 sf_caltcp:1, 866 sf_end:1, 867 sf_intr:1, 868 sf_id:4; 869 u_int32_t sf_addrlo; 870 u_int32_t sf_addrhi; 871 }; 872 873 /* TX buffer descriptor type 3 is not defined. */ 874 875 /* 876 * TX frame descriptor type 4, 32-bit addressing. This is a special 877 * case of the type 0 descriptor, identical except that the fragment 878 * address and length fields are ordered differently. This is done 879 * to optimize copies in MS-DOS and OS/2 drivers. 880 */ 881 struct sf_tx_bufdesc_type4 { 882 #ifndef __LP64__ 883 u_int32_t sf_pad; 884 #endif 885 struct mbuf *sf_mbuf; 886 u_int32_t sf_rsvd0:24, 887 sf_crcen:1, 888 sf_caltcp:1, 889 sf_end:1, 890 sf_intr:1, 891 sf_id:4; 892 u_int8_t sf_fragcnt; 893 u_int8_t sf_rsvd2; 894 u_int16_t sf_rsvd1; 895 struct sf_frag_msdos sf_frags[14]; 896 }; 897 898 /* 899 * Transmit completion queue descriptor formats. 900 */ 901 902 /* 903 * Transmit DMA completion descriptor, type 0. 904 */ 905 #define SF_TXCMPTYPE_DMA 0x4 906 struct sf_tx_cmpdesc_type0 { 907 u_int32_t sf_index:15, 908 sf_priority:1, 909 sf_timestamp:13, 910 sf_type:3; 911 }; 912 913 /* 914 * Transmit completion descriptor, type 1. 915 */ 916 #define SF_TXCMPTYPE_TX 0x5 917 struct sf_tx_cmpdesc_type1 { 918 u_int32_t sf_index:15, 919 sf_priority:1, 920 sf_txstat:13, 921 sf_type:3; 922 }; 923 924 #define SF_TXSTAT_CRCERR 0x0001 925 #define SF_TXSTAT_LENCHECKERR 0x0002 926 #define SF_TXSTAT_LENRANGEERR 0x0004 927 #define SF_TXSTAT_TX_OK 0x0008 928 #define SF_TXSTAT_TX_DEFERED 0x0010 929 #define SF_TXSTAT_EXCESS_DEFER 0x0020 930 #define SF_TXSTAT_EXCESS_COLL 0x0040 931 #define SF_TXSTAT_LATE_COLL 0x0080 932 #define SF_TXSTAT_TOOBIG 0x0100 933 #define SF_TXSTAT_TX_UNDERRUN 0x0200 934 #define SF_TXSTAT_CTLFRAME_OK 0x0400 935 #define SF_TXSTAT_PAUSEFRAME_OK 0x0800 936 #define SF_TXSTAT_PAUSED 0x1000 937 938 /* Statistics counters. */ 939 struct sf_stats { 940 u_int32_t sf_tx_frames; 941 u_int32_t sf_tx_single_colls; 942 u_int32_t sf_tx_multi_colls; 943 u_int32_t sf_tx_crcerrs; 944 u_int32_t sf_tx_bytes; 945 u_int32_t sf_tx_defered; 946 u_int32_t sf_tx_late_colls; 947 u_int32_t sf_tx_pause_frames; 948 u_int32_t sf_tx_control_frames; 949 u_int32_t sf_tx_excess_colls; 950 u_int32_t sf_tx_excess_defer; 951 u_int32_t sf_tx_mcast_frames; 952 u_int32_t sf_tx_bcast_frames; 953 u_int32_t sf_tx_frames_lost; 954 u_int32_t sf_rx_rx_frames; 955 u_int32_t sf_rx_crcerrs; 956 u_int32_t sf_rx_alignerrs; 957 u_int32_t sf_rx_bytes; 958 u_int32_t sf_rx_control_frames; 959 u_int32_t sf_rx_unsup_control_frames; 960 u_int32_t sf_rx_giants; 961 u_int32_t sf_rx_runts; 962 u_int32_t sf_rx_jabbererrs; 963 u_int32_t sf_rx_pkts_64; 964 u_int32_t sf_rx_pkts_65_127; 965 u_int32_t sf_rx_pkts_128_255; 966 u_int32_t sf_rx_pkts_256_511; 967 u_int32_t sf_rx_pkts_512_1023; 968 u_int32_t sf_rx_pkts_1024_1518; 969 u_int32_t sf_rx_frames_lost; 970 u_int16_t sf_tx_underruns; 971 u_int16_t sf_pad; 972 }; 973 974 /* 975 * register space access macros 976 */ 977 #define CSR_WRITE_4(sc, reg, val) \ 978 bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val) 979 980 #define CSR_READ_4(sc, reg) \ 981 bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg) 982 983 #define CSR_READ_1(sc, reg) \ 984 bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg) 985 986 987 struct sf_type { 988 u_int16_t sf_vid; 989 u_int16_t sf_did; 990 char *sf_name; 991 }; 992 993 #define SF_INC(x, y) (x) = (x + 1) % y 994 995 #define ETHER_ALIGN 2 996 997 /* 998 * Note: alignment is important here: each list must be aligned to 999 * a 256-byte boundary. It turns out that each ring is some multiple 1000 * of 4K in length, so we can stack them all on top of each other 1001 * and just worry about aligning the whole mess. There's one transmit 1002 * buffer ring and two receive buffer rings: one RX ring is for small 1003 * packets and the other is for large packets. Each buffer ring also 1004 * has a companion completion queue. 1005 */ 1006 struct sf_list_data { 1007 struct sf_tx_bufdesc_type0 sf_tx_dlist[SF_TX_DLIST_CNT]; 1008 struct sf_tx_cmpdesc_type1 sf_tx_clist[SF_TX_CLIST_CNT]; 1009 struct sf_rx_bufdesc_type0 sf_rx_dlist_big[SF_RX_DLIST_CNT]; 1010 #ifdef notdef 1011 /* 1012 * Unfortunately, because the Starfire doesn't allow arbitrary 1013 * byte alignment, we have to copy packets in the RX handler in 1014 * order to align the payload correctly. This means that we 1015 * don't gain anything by having separate large and small descriptor 1016 * lists, so for now we don't bother with the small one. 1017 */ 1018 struct sf_rx_bufdesc_type0 sf_rx_dlist_small[SF_RX_DLIST_CNT]; 1019 #endif 1020 struct sf_rx_cmpdesc_type3 sf_rx_clist[SF_RX_CLIST_CNT]; 1021 }; 1022 1023 struct sf_softc { 1024 struct arpcom arpcom; /* interface info */ 1025 bus_space_handle_t sf_bhandle; /* bus space handle */ 1026 bus_space_tag_t sf_btag; /* bus space tag */ 1027 void *sf_intrhand; /* interrupt handler cookie */ 1028 struct resource *sf_irq; /* irq resource descriptor */ 1029 struct resource *sf_res; /* mem/ioport resource */ 1030 struct sf_type *sf_info; /* Starfire adapter info */ 1031 device_t sf_miibus; 1032 u_int8_t sf_unit; /* interface number */ 1033 struct sf_list_data *sf_ldata; 1034 int sf_tx_cnt; 1035 u_int8_t sf_link; 1036 int sf_if_flags; 1037 struct callout sf_stat_timer; 1038 }; 1039 1040 #define SF_TIMEOUT 1000 1041