Searched refs:READ_ONCE (Results 1 – 25 of 38) sorted by relevance
12
63 typeof(*(p)) *__rcu_dereference_tmp = READ_ONCE(p); \68 ((__typeof(*p) *)READ_ONCE(p))90 #define rcu_access_pointer(p) ((typeof(*p) *)READ_ONCE(p))
93 return READ_ONCE(sl->sequence); in read_seqbegin()119 ret = READ_ONCE(s->sequence); in __read_seqcount_begin()167 unsigned int value = READ_ONCE(s->sequence); in raw_read_seqcount()
100 return READ_ONCE(v->counter); in atomic_read()207 int val = READ_ONCE(v->counter); in atomic_fetch_xor()
66 struct llist_node *first = READ_ONCE(head->first); in llist_add()
145 if (READ_ONCE(c->done) == 0) in try_wait_for_completion()
131 #define READ_ONCE(x) ({ \ macro
96 node = READ_ONCE(queue->head); in spsc_queue_pop()101 next = READ_ONCE(node->next); in spsc_queue_pop()112 } while (unlikely(!(queue->head = READ_ONCE(node->next)))); in spsc_queue_pop()
49 desc_phase = (READ_ONCE(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> in ena_com_get_next_rx_cdesc()248 last = (READ_ONCE(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> in ena_com_cdesc_rx_pkt_get()610 cdesc_phase = READ_ONCE(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK; in ena_com_tx_comp_req_id_get()621 *req_id = READ_ONCE(cdesc->req_id); in ena_com_tx_comp_req_id_get()
370 #define READ_ONCE(x) ({ \ macro
396 WARN_ON(READ_ONCE(vblank->enabled) && in drm_vblank_cleanup()1363 if (!READ_ONCE(vblank->enabled)) { in drm_queue_vblank_event()1507 READ_ONCE(vblank->enabled)) { in drm_wait_vblank_ioctl()1553 !READ_ONCE(vblank->enabled)); in drm_wait_vblank_ioctl()1710 vblank_enabled = dev->vblank_disable_immediate && READ_ONCE(vblank->enabled); in drm_crtc_get_sequence_ioctl()1807 if (!READ_ONCE(vblank->enabled)) { in drm_crtc_queue_sequence_ioctl()
586 return READ_ONCE(engine->status_page.page_addr[reg]); in intel_read_status_page()755 return READ_ONCE(engine->timeline->seqno); in intel_engine_last_submit()841 return READ_ONCE(engine->breadcrumbs.irq_wait); in intel_engine_has_waiter()
382 return READ_ONCE(obj->framebuffer_references); in i915_gem_object_is_framebuffer()
437 wq_off = READ_ONCE(desc->tail); in guc_wq_item_append()438 GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head), in guc_wq_item_append()479 cookie = READ_ONCE(db->cookie); in guc_ring_doorbell()
548 GEM_BUG_ON(READ_ONCE(b->irq_wait) == wait); in intel_engine_remove_wait()846 WARN_ON(READ_ONCE(b->irq_wait)); in intel_engine_fini_breadcrumbs()
424 READ_ONCE(obj->tiling_and_stride) & TILING_MASK; in i915_gem_get_tiling_ioctl()
279 return READ_ONCE(request->global_seqno); in i915_gem_request_global_seqno()
102 if (READ_ONCE(obj->pin_global)) in can_release_pages()
434 if (!READ_ONCE(dev_priv->gt.awake)) in i915_hangcheck_elapsed()
827 tail = READ_ONCE(buf[write_idx]); in intel_lrc_irq_handler()855 status = READ_ONCE(buf[2 * head]); /* maybe mmio! */ in intel_lrc_irq_handler()992 if (prio <= READ_ONCE(request->priotree.priority)) in execlists_schedule()1031 if (prio > READ_ONCE(p->signaler->priority)) in execlists_schedule()
1557 if (READ_ONCE(engine->execlists.active)) in intel_engine_is_idle()1561 if (READ_ONCE(engine->execlists.first)) in intel_engine_is_idle()1576 if (READ_ONCE(dev_priv->gt.active_requests)) in intel_engines_are_idle()
342 #define done (READ_ONCE(desc->fence) == fence) in wait_for_response()
535 enabled = READ_ONCE(dev_priv->hotplug.poll_enabled); in i915_hpd_poll_init_work()
294 uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq); in amdgpu_fence_wait_empty()358 emitted += READ_ONCE(ring->fence_drv.sync_seq); in amdgpu_fence_count_emitted()
832 pin_count = READ_ONCE(bo->pin_count); in amdgpu_debugfs_gem_bo_info()836 dma_buf = READ_ONCE(bo->gem_base.dma_buf); in amdgpu_debugfs_gem_bo_info()837 attachment = READ_ONCE(bo->gem_base.import_attach); in amdgpu_debugfs_gem_bo_info()
463 cur_placement = READ_ONCE(robj->tbo.mem.mem_type); in radeon_gem_busy_ioctl()493 cur_placement = READ_ONCE(robj->tbo.mem.mem_type); in radeon_gem_wait_idle_ioctl()