Searched refs:RADEON_VCLK_ECP_CNTL (Results 1 – 4 of 4) sorted by relevance
522 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()525 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()575 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()578 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()728 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()732 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()764 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()768 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()815 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()819 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()[all …]
948 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, in radeon_set_pll()1020 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, in radeon_set_pll()
659 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_primary_dac_detect()667 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_primary_dac_detect()710 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); in radeon_legacy_primary_dac_detect()
1784 #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ macro