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Searched refs:PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h8185 #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x00000001L macro
HDdce_8_0_sh_mask.h43 #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 macro
HDdce_10_0_sh_mask.h43 #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 macro
HDdce_11_0_sh_mask.h43 #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 macro
HDdce_11_2_sh_mask.h43 #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 macro
HDdce_12_0_sh_mask.h3310 #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK … macro