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Searched refs:PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_sh_mask.h8170 #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x0000001e macro
HDdce_8_0_sh_mask.h40 #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e macro
HDdce_10_0_sh_mask.h40 #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e macro
HDdce_11_0_sh_mask.h40 #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e macro
HDdce_11_2_sh_mask.h40 #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e macro
HDdce_12_0_sh_mask.h3302 #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT … macro