1 /* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/pci/if_pcnreg.h,v 1.3.2.3 2001/02/21 22:13:07 wpaul Exp $ 34 * $DragonFly: src/sys/dev/netif/pcn/if_pcnreg.h,v 1.5 2006/08/01 18:06:14 swildner Exp $ 35 */ 36 37 /* 38 * I/O map in 16-bit mode. To switch to 32-bit mode, 39 * you need to perform a 32-bit write to the RDP register 40 * (writing a 0 is recommended). 41 */ 42 #define PCN_IO16_APROM00 0x00 43 #define PCN_IO16_APROM01 0x02 44 #define PCN_IO16_APROM02 0x04 45 #define PCN_IO16_APROM03 0x06 46 #define PCN_IO16_APROM04 0x08 47 #define PCN_IO16_APROM05 0x0A 48 #define PCN_IO16_APROM06 0x0C 49 #define PCN_IO16_APROM07 0x0E 50 #define PCN_IO16_RDP 0x10 51 #define PCN_IO16_RAP 0x12 52 #define PCN_IO16_RESET 0x14 53 #define PCN_IO16_BDP 0x16 54 55 /* 56 * I/O map in 32-bit mode. 57 */ 58 #define PCN_IO32_APROM00 0x00 59 #define PCN_IO32_APROM01 0x04 60 #define PCN_IO32_APROM02 0x08 61 #define PCN_IO32_APROM03 0x0C 62 #define PCN_IO32_RDP 0x10 63 #define PCN_IO32_RAP 0x14 64 #define PCN_IO32_RESET 0x18 65 #define PCN_IO32_BDP 0x1C 66 67 /* 68 * CSR registers 69 */ 70 #define PCN_CSR_CSR 0x00 71 #define PCN_CSR_IAB0 0x01 72 #define PCN_CSR_IAB1 0x02 73 #define PCN_CSR_IMR 0x03 74 #define PCN_CSR_TFEAT 0x04 75 #define PCN_CSR_EXTCTL1 0x05 76 #define PCN_CSR_DTBLLEN 0x06 77 #define PCN_CSR_EXTCTL2 0x07 78 #define PCN_CSR_MAR0 0x08 79 #define PCN_CSR_MAR1 0x09 80 #define PCN_CSR_MAR2 0x0A 81 #define PCN_CSR_MAR3 0x0B 82 #define PCN_CSR_PAR0 0x0C 83 #define PCN_CSR_PAR1 0x0D 84 #define PCN_CSR_PAR2 0x0E 85 #define PCN_CSR_MODE 0x0F 86 #define PCN_CSR_RXADDR0 0x18 87 #define PCN_CSR_RXADDR1 0x19 88 #define PCN_CSR_TXADDR0 0x1E 89 #define PCN_CSR_TXADDR1 0x1F 90 #define PCN_CSR_TXPOLL 0x2F 91 #define PCN_CSR_RXPOLL 0x31 92 #define PCN_CSR_RXRINGLEN 0x4C 93 #define PCN_CSR_TXRINGLEN 0x4E 94 #define PCN_CSR_DMACTL 0x50 95 #define PCN_CSR_BUSTIMER 0x52 96 #define PCN_CSR_MEMERRTIMEO 0x64 97 #define PCN_CSR_ONNOWMISC 0x74 98 #define PCN_CSR_ADVFEAT 0x7A 99 #define PCN_CSR_MACCFG 0x7D 100 #define PCN_CSR_CHIPID0 0x58 101 #define PCN_CSR_CHIPID1 0x59 102 103 /* 104 * Control and status register (CSR0) 105 */ 106 #define PCN_CSR_INIT 0x0001 107 #define PCN_CSR_START 0x0002 108 #define PCN_CSR_STOP 0x0004 109 #define PCN_CSR_TX 0x0008 110 #define PCN_CSR_TXON 0x0010 111 #define PCN_CSR_RXON 0x0020 112 #define PCN_CSR_INTEN 0x0040 113 #define PCN_CSR_INTR 0x0080 114 #define PCN_CSR_IDONE 0x0100 115 #define PCN_CSR_TINT 0x0200 116 #define PCN_CSR_RINT 0x0400 117 #define PCN_CSR_MERR 0x0800 118 #define PCN_CSR_MISS 0x1000 119 #define PCN_CSR_CERR 0x2000 120 #define PCN_CSR_ERR 0x8000 121 122 /* 123 * Interrupt masks and deferral control (CSR3) 124 */ 125 #define PCN_IMR_BSWAP 0x0004 126 #define PCN_IMR_ENMBA 0x0008 /* enable modified backoff alg */ 127 #define PCN_IMR_DXMT2PD 0x0010 128 #define PCN_IMR_LAPPEN 0x0020 /* lookahead packet processing enb */ 129 #define PCN_IMR_DXSUFLO 0x0040 /* disable TX stop on underflow */ 130 #define PCN_IMR_IDONE 0x0100 131 #define PCN_IMR_TINT 0x0200 132 #define PCN_IMR_RINT 0x0400 133 #define PCN_IMR_MERR 0x0800 134 #define PCN_IMR_MISS 0x1000 135 136 /* 137 * Test and features control (CSR4) 138 */ 139 #define PCN_TFEAT_TXSTRTMASK 0x0004 140 #define PCN_TFEAT_TXSTRT 0x0008 141 #define PCN_TFEAT_RXCCOFLOWM 0x0010 /* Rx collision counter oflow */ 142 #define PCN_TFEAT_RXCCOFLOW 0x0020 143 #define PCN_TFEAT_UINT 0x0040 144 #define PCN_TFEAT_UINTREQ 0x0080 145 #define PCN_TFEAT_MISSOFLOWM 0x0100 146 #define PCN_TFEAT_MISSOFLOW 0x0200 147 #define PCN_TFEAT_STRIP_FCS 0x0400 148 #define PCN_TFEAT_PAD_TX 0x0800 149 #define PCN_TFEAT_TXDPOLL 0x1000 150 #define PCN_TFEAT_DMAPLUS 0x4000 151 152 /* 153 * Extended control and interrupt 1 (CSR5) 154 */ 155 #define PCN_EXTCTL1_SPND 0x0001 /* suspend */ 156 #define PCN_EXTCTL1_MPMODE 0x0002 /* magic packet mode */ 157 #define PCN_EXTCTL1_MPENB 0x0004 /* magic packet enable */ 158 #define PCN_EXTCTL1_MPINTEN 0x0008 /* magic packet interrupt enable */ 159 #define PCN_EXTCTL1_MPINT 0x0010 /* magic packet interrupt */ 160 #define PCN_EXTCTL1_MPPLBA 0x0020 /* magic packet phys. logical bcast */ 161 #define PCN_EXTCTL1_EXDEFEN 0x0040 /* excessive deferral interrupt enb. */ 162 #define PCN_EXTCTL1_EXDEF 0x0080 /* excessive deferral interrupt */ 163 #define PCN_EXTCTL1_SINTEN 0x0400 /* system interrupt enable */ 164 #define PCN_EXTCTL1_SINT 0x0800 /* system interrupt */ 165 #define PCN_EXTCTL1_LTINTEN 0x4000 /* last TX interrupt enb */ 166 #define PCN_EXTCTL1_TXOKINTD 0x8000 /* TX OK interrupt disable */ 167 168 /* 169 * RX/TX descriptor len (CSR6) 170 */ 171 #define PCN_DTBLLEN_RLEN 0x0F00 172 #define PCN_DTBLLEN_TLEN 0xF000 173 174 /* 175 * Extended control and interrupt 2 (CSR7) 176 */ 177 #define PCN_EXTCTL2_MIIPDTINTE 0x0001 178 #define PCN_EXTCTL2_MIIPDTINT 0x0002 179 #define PCN_EXTCTL2_MCCIINTE 0x0004 180 #define PCN_EXTCTL2_MCCIINT 0x0008 181 #define PCN_EXTCTL2_MCCINTE 0x0010 182 #define PCN_EXTCTL2_MCCINT 0x0020 183 #define PCN_EXTCTL2_MAPINTE 0x0040 184 #define PCN_EXTCTL2_MAPINT 0x0080 185 #define PCN_EXTCTL2_MREINTE 0x0100 186 #define PCN_EXTCTL2_MREINT 0x0200 187 #define PCN_EXTCTL2_STINTE 0x0400 188 #define PCN_EXTCTL2_STINT 0x0800 189 #define PCN_EXTCTL2_RXDPOLL 0x1000 190 #define PCN_EXTCTL2_RDMD 0x2000 191 #define PCN_EXTCTL2_RXFRTG 0x4000 192 #define PCN_EXTCTL2_FASTSPNDE 0x8000 193 194 195 /* 196 * Mode (CSR15) 197 */ 198 #define PCN_MODE_RXD 0x0001 /* RX disable */ 199 #define PCN_MODE_TXD 0x0002 /* TX disable */ 200 #define PCN_MODE_LOOP 0x0004 /* loopback enable */ 201 #define PCN_MODE_TXCRCD 0x0008 202 #define PCN_MODE_FORCECOLL 0x0010 203 #define PCN_MODE_RETRYD 0x0020 204 #define PCN_MODE_INTLOOP 0x0040 205 #define PCN_MODE_PORTSEL 0x0180 206 #define PCN_MODE_RXVPAD 0x2000 207 #define PCN_MODE_RXNOBROAD 0x4000 208 #define PCN_MODE_PROMISC 0x8000 209 210 #define PCN_PORT_GPSI 0x0100 211 #define PCN_PORT_MII 0x0180 212 213 /* 214 * Chip ID values. 215 */ 216 /* CSR88-89: Chip ID masks */ 217 #define AMD_MASK 0x003 218 #define PART_MASK 0xffff 219 #define Am79C960 0x0003 220 #define Am79C961 0x2260 221 #define Am79C961A 0x2261 222 #define Am79C965 0x2430 223 #define Am79C970 0x0242 224 #define Am79C970A 0x2621 225 #define Am79C971 0x2623 226 #define Am79C972 0x2624 227 #define Am79C973 0x2625 228 #define Am79C978 0x2626 229 #define Am79C975 0x2627 230 #define Am79C976 0x2628 231 232 /* 233 * Advanced feature control (CSR122) 234 */ 235 #define PCN_AFC_RXALIGN 0x0001 236 237 /* 238 * BCR (bus control) registers 239 */ 240 #define PCN_BCR_MISCCFG 0x02 241 #define PCN_BCR_LED0 0x04 242 #define PCN_BCR_LED1 0x05 243 #define PCN_BCR_LED2 0x06 244 #define PCN_BCR_LED3 0x07 245 #define PCN_BCR_DUPLEX 0x09 246 #define PCN_BCR_BUSCTL 0x12 247 #define PCN_BCR_EECTL 0x13 248 #define PCN_BCR_SSTYLE 0x14 249 #define PCN_BCR_PCILAT 0x16 250 #define PCN_BCR_PCISUBVENID 0x17 251 #define PCN_BCR_PCISUBSYSID 0x18 252 #define PCN_BCR_SRAMSIZE 0x19 253 #define PCN_BCR_SRAMBOUND 0x1A 254 #define PCN_BCR_SRAMCTL 0x1B 255 #define PCN_BCR_MIICTL 0x20 256 #define PCN_BCR_MIIADDR 0x21 257 #define PCN_BCR_MIIDATA 0x22 258 #define PCN_BCR_PCIVENID 0x23 259 #define PCN_BCR_PCIPCAP 0x24 260 #define PCN_BCR_DATA0 0x25 261 #define PCN_BCR_DATA1 0x26 262 #define PCN_BCR_DATA2 0x27 263 #define PCN_BCR_DATA3 0x28 264 #define PCN_BCR_DATA4 0x29 265 #define PCN_BCR_DATA5 0x2A 266 #define PCN_BCR_DATA6 0x2B 267 #define PCN_BCR_DATA7 0x2C 268 #define PCN_BCR_ONNOWPAT0 0x2D 269 #define PCN_BCR_ONNOWPAT1 0x2E 270 #define PCN_BCR_ONNOWPAT2 0x2F 271 #define PCN_BCR_PHYSEL 0x31 272 273 /* 274 * Full duplex control (BCR9) 275 */ 276 #define PCN_DUPLEX_FDEN 0x0001 /* Full-duplex enable */ 277 #define PCN_DUPLEX_FDRPAD 0x0004 /* Full-duplex runt pkt accept dis. */ 278 279 /* 280 * Burst and bus control register (BCR18) 281 */ 282 #define PCN_BUSCTL_BWRITE 0x0020 283 #define PCN_BUSCTL_BREAD 0x0040 284 #define PCN_BUSCTL_DWIO 0x0080 285 #define PCN_BUSCTL_EXTREQ 0x0100 286 #define PCN_BUSCTL_MEMCMD 0x0200 287 #define PCN_BUSCTL_NOUFLOW 0x0800 288 #define PCN_BUSCTL_ROMTMG 0xF000 289 290 /* 291 * EEPROM control (BCR19) 292 */ 293 #define PCN_EECTL_EDATA 0x0001 294 #define PCN_EECTL_ECLK 0x0002 295 #define PCN_EECTL_EECS 0x0004 296 #define PCN_EECTL_EEN 0x0100 297 #define PCN_EECTL_EEDET 0x2000 298 #define PCN_EECTL_PREAD 0x4000 299 #define PCN_EECTL_PVALID 0x8000 300 301 /* 302 * Software style (BCR20) 303 */ 304 #define PCN_SSTYLE_APERREN 0x0400 /* advanced parity error checking */ 305 #define PCN_SSTYLE_SSIZE32 0x0100 306 #define PCN_SSTYLE_SWSTYLE 0x00FF 307 308 #define PCN_SWSTYLE_LANCE 0x0000 309 #define PCN_SWSTYLE_PCNETPCI 0x0102 310 #define PCN_SWSTYLE_PCNETPCI_BURST 0x0103 311 312 /* 313 * MII control and status (BCR32) 314 */ 315 #define PCN_MIICTL_MIILP 0x0002 /* MII internal loopback */ 316 #define PCN_MIICTL_XPHYSP 0x0008 /* external PHY speed */ 317 #define PCN_MIICTL_XPHYFD 0x0010 /* external PHY full duplex */ 318 #define PCN_MIICTL_XPHYANE 0x0020 /* external phy auto-neg enable */ 319 #define PCN_MIICTL_XPHYRST 0x0040 /* external PHY reset */ 320 #define PCN_MIICTL_DANAS 0x0080 /* disable auto-neg auto-setup */ 321 #define PCN_MIICTL_APDW 0x0700 /* auto-poll dwell time */ 322 #define PCN_MIICTL_APEP 0x0100 /* auto-poll external PHY */ 323 #define PCN_MIICTL_FMDC 0x3000 /* data clock speed */ 324 #define PCN_MIICTL_MIIPD 0x4000 /* PHY detect */ 325 #define PCN_MIICTL_ANTST 0x8000 /* Manufacturing test */ 326 327 /* 328 * MII address register (BCR33) 329 */ 330 #define PCN_MIIADDR_REGAD 0x001F 331 #define PCN_MIIADDR_PHYADD 0x03E0 332 333 /* 334 * MII data register (BCR34) 335 */ 336 #define PCN_MIIDATA_MIIMD 0xFFFF 337 338 /* 339 * PHY selection (BCR49) (HomePNA NIC only) 340 */ 341 #define PCN_PHYSEL_PHYSEL 0x0003 342 #define PCN_PHYSEL_DEFAULT 0x0300 343 #define PCN_PHYSEL_PCNET 0x8000 344 345 #define PCN_PHY_10BT 0x0000 346 #define PCN_PHY_HOMEPNA 0x0001 347 #define PCN_PHY_EXTERNAL 0x0002 348 349 struct pcn_rx_desc { 350 u_int16_t pcn_rxlen; 351 u_int16_t pcn_rsvd0; 352 u_int16_t pcn_bufsz; 353 u_int16_t pcn_rxstat; 354 u_int32_t pcn_rbaddr; 355 u_int32_t pcn_uspace; 356 }; 357 358 #define PCN_RXSTAT_BPE 0x0080 /* bus parity error */ 359 #define PCN_RXSTAT_ENP 0x0100 /* end of packet */ 360 #define PCN_RXSTAT_STP 0x0200 /* start of packet */ 361 #define PCN_RXSTAT_BUFF 0x0400 /* buffer error */ 362 #define PCN_RXSTAT_CRC 0x0800 /* CRC error */ 363 #define PCN_RXSTAT_OFLOW 0x1000 /* rx overrun */ 364 #define PCN_RXSTAT_FRAM 0x2000 /* framing error */ 365 #define PCN_RXSTAT_ERR 0x4000 /* error summary */ 366 #define PCN_RXSTAT_OWN 0x8000 367 368 #define PCN_RXLEN_MBO 0xF000 369 #define PCN_RXLEN_BUFSZ 0x0FFF 370 371 #define PCN_OWN_RXDESC(x) (((x)->pcn_rxstat & PCN_RXSTAT_OWN) == 0) 372 373 struct pcn_tx_desc { 374 u_int32_t pcn_txstat; 375 u_int32_t pcn_txctl; 376 u_int32_t pcn_tbaddr; 377 u_int32_t pcn_uspace; 378 }; 379 380 #define PCN_TXSTAT_TRC 0x0000000F /* transmit retries */ 381 #define PCN_TXSTAT_RTRY 0x04000000 /* retry */ 382 #define PCN_TXSTAT_LCAR 0x08000000 /* lost carrier */ 383 #define PCN_TXSTAT_LCOL 0x10000000 /* late collision */ 384 #define PCN_TXSTAT_EXDEF 0x20000000 /* excessive deferrals */ 385 #define PCN_TXSTAT_UFLOW 0x40000000 /* transmit underrun */ 386 #define PCN_TXSTAT_BUFF 0x80000000 /* buffer error */ 387 388 #define PCN_TXCTL_OWN 0x80000000 389 #define PCN_TXCTL_ERR 0x40000000 /* error summary */ 390 #define PCN_TXCTL_ADD_FCS 0x20000000 /* add FCS to pkt */ 391 #define PCN_TXCTL_MORE_LTINT 0x10000000 392 #define PCN_TXCTL_ONE 0x08000000 393 #define PCN_TXCTL_DEF 0x04000000 394 #define PCN_TXCTL_STP 0x02000000 395 #define PCN_TXCTL_ENP 0x01000000 396 #define PCN_TXCTL_BPE 0x00800000 397 #define PCN_TXCTL_MBO 0x0000F000 398 #define PCN_TXCTL_BUFSZ 0x00000FFF 399 400 #define PCN_OWN_TXDESC(x) (((x)->pcn_txctl & PCN_TXCTL_OWN) == 0) 401 402 #define PCN_RX_LIST_CNT 64 403 #define PCN_TX_LIST_CNT 256 404 405 struct pcn_list_data { 406 struct pcn_rx_desc pcn_rx_list[PCN_RX_LIST_CNT]; 407 struct pcn_tx_desc pcn_tx_list[PCN_TX_LIST_CNT]; 408 }; 409 410 struct pcn_ring_data { 411 struct mbuf *pcn_rx_chain[PCN_RX_LIST_CNT]; 412 struct mbuf *pcn_tx_chain[PCN_TX_LIST_CNT]; 413 int pcn_rx_prod; 414 int pcn_tx_prod; 415 int pcn_tx_cons; 416 int pcn_tx_cnt; 417 }; 418 419 struct pcn_type { 420 u_int16_t pcn_vid; 421 u_int16_t pcn_did; 422 char *pcn_name; 423 }; 424 425 struct pcn_softc { 426 struct arpcom arpcom; /* interface info */ 427 bus_space_handle_t pcn_bhandle; 428 bus_space_tag_t pcn_btag; 429 struct resource *pcn_res; 430 struct resource *pcn_irq; 431 void *pcn_intrhand; 432 device_t pcn_miibus; 433 u_int8_t pcn_unit; 434 u_int8_t pcn_link; 435 u_int8_t pcn_phyaddr; 436 int pcn_if_flags; 437 int pcn_type; 438 struct pcn_list_data *pcn_ldata; 439 struct pcn_ring_data pcn_cdata; 440 struct callout pcn_stat_timer; 441 }; 442 443 /* 444 * register space access macros 445 */ 446 #define CSR_WRITE_4(sc, reg, val) \ 447 bus_space_write_4(sc->pcn_btag, sc->pcn_bhandle, reg, val) 448 449 #define CSR_READ_4(sc, reg) \ 450 bus_space_read_4(sc->pcn_btag, sc->pcn_bhandle, reg) 451 452 #define CSR_WRITE_2(sc, reg, val) \ 453 bus_space_write_2(sc->pcn_btag, sc->pcn_bhandle, reg, val) 454 455 #define CSR_READ_2(sc, reg) \ 456 bus_space_read_2(sc->pcn_btag, sc->pcn_bhandle, reg) 457 458 459 #define PCN_TIMEOUT 1000 460 #define ETHER_ALIGN 2 461 #define PCN_RXLEN 1536 462 #define PCN_MIN_FRAMELEN 60 463 #define PCN_INC(x, y) (x) = (x + 1) % y 464 /* 465 * PCI low memory base and low I/O base register, and 466 * other PCI registers. 467 */ 468 469 #define PCN_PCI_VENDOR_ID 0x00 470 #define PCN_PCI_DEVICE_ID 0x02 471 #define PCN_PCI_COMMAND 0x04 472 #define PCN_PCI_STATUS 0x06 473 #define PCN_PCI_REVID 0x08 474 #define PCN_PCI_CLASSCODE 0x09 475 #define PCN_PCI_CACHELEN 0x0C 476 #define PCN_PCI_LATENCY_TIMER 0x0D 477 #define PCN_PCI_HEADER_TYPE 0x0E 478 #define PCN_PCI_LOIO 0x10 479 #define PCN_PCI_LOMEM 0x14 480 #define PCN_PCI_BIOSROM 0x30 481 #define PCN_PCI_INTLINE 0x3C 482 #define PCN_PCI_INTPIN 0x3D 483 #define PCN_PCI_MINGNT 0x3E 484 #define PCN_PCI_MINLAT 0x0F 485 #define PCN_PCI_RESETOPT 0x48 486 #define PCN_PCI_EEPROM_DATA 0x4C 487 488 /* power management registers */ 489 #define PCN_PCI_CAPID 0x50 /* 8 bits */ 490 #define PCN_PCI_NEXTPTR 0x51 /* 8 bits */ 491 #define PCN_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 492 #define PCN_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 493 494 #define PCN_PSTATE_MASK 0x0003 495 #define PCN_PSTATE_D0 0x0000 496 #define PCN_PSTATE_D1 0x0001 497 #define PCN_PSTATE_D2 0x0002 498 #define PCN_PSTATE_D3 0x0003 499 #define PCN_PME_EN 0x0010 500 #define PCN_PME_STATUS 0x8000 501