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Searched refs:PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h6876 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L macro
HDgfx_7_2_sh_mask.h5789 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 macro
HDgfx_8_1_sh_mask.h7111 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 macro
HDgfx_8_0_sh_mask.h6577 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h21360 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … macro
HDgc_9_2_1_sh_mask.h22741 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK … macro