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Searched refs:PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h5970 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L macro
HDgfx_7_2_sh_mask.h5465 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4 macro
HDgfx_8_1_sh_mask.h6785 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4 macro
HDgfx_8_0_sh_mask.h6251 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h16846 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK … macro
HDgc_9_2_1_sh_mask.h18157 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK … macro