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Searched refs:PA_CL_UCP_3_W__DATA_REGISTER_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h5694 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffffL macro
HDgfx_7_2_sh_mask.h5641 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff macro
HDgfx_8_1_sh_mask.h6963 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff macro
HDgfx_8_0_sh_mask.h6429 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h15380 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK … macro
HDgc_9_2_1_sh_mask.h16686 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK … macro