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Searched refs:PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h5685 #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x00000000 macro
HDgfx_7_2_sh_mask.h5624 #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 macro
HDgfx_8_1_sh_mask.h6946 #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 macro
HDgfx_8_0_sh_mask.h6412 #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h15352 #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT … macro
HDgc_9_2_1_sh_mask.h16658 #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT … macro