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Searched refs:PA_CL_UCP_1_X__DATA_REGISTER_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h5680 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffffL macro
HDgfx_7_2_sh_mask.h5619 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff macro
HDgfx_8_1_sh_mask.h6941 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff macro
HDgfx_8_0_sh_mask.h6407 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h15347 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK … macro
HDgc_9_2_1_sh_mask.h16653 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK … macro