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Searched refs:PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h5620 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L macro
HDgfx_7_2_sh_mask.h5675 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20 macro
HDgfx_8_1_sh_mask.h6997 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20 macro
HDgfx_8_0_sh_mask.h6463 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h1550 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK … macro
HDgc_9_2_1_sh_mask.h1480 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK … macro