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Searched refs:PA_CL_CLIP_CNTL__UCP_ENA_0_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h5582 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L macro
HDgfx_7_2_sh_mask.h5565 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 macro
HDgfx_8_1_sh_mask.h6887 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 macro
HDgfx_8_0_sh_mask.h6353 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h16783 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK … macro
HDgc_9_2_1_sh_mask.h18093 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK … macro