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Searched refs:PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (Results 1 – 13 of 13) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDsoc15d.h208 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
HDvid.h270 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
HDcikd.h388 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
HDgfx_v9_0.c781 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v9_0_get_csb_buffer()
2410 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v9_0_cp_gfx_start()
HDgfx_v8_0.c1270 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_get_csb_buffer()
4395 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
/dragonfly/sys/dev/drm/radeon/
HDnid.h1262 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
HDsid.h1776 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
HDcikd.h1854 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
HDevergreend.h1657 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
HDni.c1588 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cayman_cp_start()
HDsi.c3583 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_cp_start()
5713 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_get_csb_buffer()
HDcik.c4037 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_cp_gfx_start()
6759 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_get_csb_buffer()
HDevergreen.c3010 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in evergreen_cp_start()