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Searched refs:MRDCK0_RESET (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDsid.h603 # define MRDCK0_RESET (1 << 16) macro
HDcikd.h728 # define MRDCK0_RESET (1 << 16) macro
HDci_dpm.c3101 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; in ci_populate_smc_acpi_level()
HDsi_dpm.c4569 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; in si_populate_smc_acpi_state()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
HDiceland_smumgr.c1511 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); in iceland_populate_smc_acpi_level()
HDtonga_smumgr.c1244 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); in tonga_populate_smc_acpi_level()
HDci_smumgr.c1463 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); in ci_populate_smc_acpi_level()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDsi_dpm.c5033 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; in si_populate_smc_acpi_state()