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Searched refs:MPLL_DQ_FUNC_CNTL (Results 1 – 15 of 15) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDrv740d.h63 #define MPLL_DQ_FUNC_CNTL 0x62c macro
HDrv740_dpm.c305 RREG32(MPLL_DQ_FUNC_CNTL); in rv740_read_clock_registers()
HDrv770d.h136 #define MPLL_DQ_FUNC_CNTL 0x62c macro
HDnid.h578 #define MPLL_DQ_FUNC_CNTL 0x62c macro
HDsid.h626 #define MPLL_DQ_FUNC_CNTL 0x2bc4 macro
HDcikd.h749 #define MPLL_DQ_FUNC_CNTL 0x2bc4 macro
HDevergreend.h116 #define MPLL_DQ_FUNC_CNTL 0x62c macro
HDrv770_dpm.c1540 RREG32(MPLL_DQ_FUNC_CNTL); in rv770_read_clock_registers()
HDni_dpm.c1191 ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ni_read_clock_registers()
HDci_dpm.c1923 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
HDsi_dpm.c3579 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in si_read_clock_registers()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
HDiceland_smumgr.c1090 … MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); in iceland_calculate_mclk_params()
1092 … MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
HDtonga_smumgr.c830 MPLL_DQ_FUNC_CNTL, YCLK_SEL, in tonga_calculate_mclk_params()
833 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, in tonga_calculate_mclk_params()
HDci_smumgr.c1062 … MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); in ci_calculate_mclk_params()
1064 … MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDsi_dpm.c4039 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in si_read_clock_registers()