1 /*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /*- 27 * Copyright (c) 2007 LSI Corp. 28 * Copyright (c) 2007 Rajesh Prabhakaran. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 * 52 * $FreeBSD: src/sys/dev/mfi/mfireg.h,v 1.16 2011/07/14 20:20:33 jhb Exp $ 53 * FreeBSD projects/head_mfi/ r232888 54 */ 55 56 #ifndef _MFIREG_H 57 #define _MFIREG_H 58 59 /* 60 * MegaRAID SAS MFI firmware definitions 61 * 62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63 * new firmware interface from the old AMI MegaRAID one, and there is no 64 * reason why this interface should be limited to just SAS. In any case, LSI 65 * seems to also call this interface 'MFI', so that will be used here. 66 */ 67 68 #define MEGAMFI_FRAME_SIZE 64 69 70 /* 71 * Start with the register set. All registers are 32 bits wide. 72 * The usual Intel IOP style setup. 73 */ 74 #define MFI_IMSG0 0x10 /* Inbound message 0 */ 75 #define MFI_IMSG1 0x14 /* Inbound message 1 */ 76 #define MFI_OMSG0 0x18 /* Outbound message 0 */ 77 #define MFI_OMSG1 0x1c /* Outbound message 1 */ 78 #define MFI_IDB 0x20 /* Inbound doorbell */ 79 #define MFI_ISTS 0x24 /* Inbound interrupt status */ 80 #define MFI_IMSK 0x28 /* Inbound interrupt mask */ 81 #define MFI_ODB 0x2c /* Outbound doorbell */ 82 #define MFI_OSTS 0x30 /* Outbound interrupt status */ 83 #define MFI_OMSK 0x34 /* Outbound interrupt mask */ 84 #define MFI_IQP 0x40 /* Inbound queue port */ 85 #define MFI_OQP 0x44 /* Outbound queue port */ 86 87 /* 88 * ThunderBolt specific Register 89 */ 90 91 #define MFI_RPI 0x6c /* reply_post_host_index */ 92 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 93 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 94 95 /* 96 * 1078 specific related register 97 */ 98 #define MFI_ODR0 0x9c /* outbound doorbell register0 */ 99 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 100 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 101 #define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ 102 #define MFI_RMI 0x2 /* reply message interrupt */ 103 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 104 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 105 106 /* OCR registers */ 107 #define MFI_WSR 0x004 /* write sequence register */ 108 #define MFI_HDR 0x008 /* host diagnostic register */ 109 #define MFI_RSR 0x3c3 /* Reset Status Register */ 110 111 /* 112 * GEN2 specific changes 113 */ 114 #define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 115 #define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 116 117 /* 118 * skinny specific changes 119 */ 120 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 121 #define MFI_IQPL 0x000000c0 122 #define MFI_IQPH 0x000000c4 123 #define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 124 125 /* Bits for MFI_OSTS */ 126 #define MFI_OSTS_INTR_VALID 0x00000002 127 128 /* OCR specific flags */ 129 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 130 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 131 132 /* 133 * Firmware state values. Found in OMSG0 during initialization. 134 */ 135 #define MFI_FWSTATE_MASK 0xf0000000 136 #define MFI_FWSTATE_UNDEFINED 0x00000000 137 #define MFI_FWSTATE_BB_INIT 0x10000000 138 #define MFI_FWSTATE_FW_INIT 0x40000000 139 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 140 #define MFI_FWSTATE_FW_INIT_2 0x70000000 141 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000 142 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 143 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 144 #define MFI_FWSTATE_READY 0xb0000000 145 #define MFI_FWSTATE_OPERATIONAL 0xc0000000 146 #define MFI_FWSTATE_FAULT 0xf0000000 147 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 148 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 149 #define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 150 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 151 #define MFI_RESET_REQUIRED 0x00000001 152 153 /* ThunderBolt Support */ 154 #define MFI_FWSTATE_TB_MASK 0xf0000000 155 #define MFI_FWSTATE_TB_RESET 0x00000000 156 #define MFI_FWSTATE_TB_READY 0x10000000 157 #define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 158 #define MFI_FWSTATE_TB_FAULT 0x40000000 159 160 /* 161 * Control bits to drive the card to ready state. These go into the IDB 162 * register. 163 */ 164 #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 165 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 166 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 167 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 168 #define MFI_FWINIT_HOTPLUG 0x00000010 169 170 /* ADP reset flags */ 171 #define MFI_STOP_ADP 0x00000020 172 #define MFI_ADP_RESET 0x00000040 173 #define DIAG_WRITE_ENABLE 0x00000080 174 #define DIAG_RESET_ADAPTER 0x00000004 175 176 /* MFI Commands */ 177 typedef enum { 178 MFI_CMD_INIT = 0x00, 179 MFI_CMD_LD_READ, 180 MFI_CMD_LD_WRITE, 181 MFI_CMD_LD_SCSI_IO, 182 MFI_CMD_PD_SCSI_IO, 183 MFI_CMD_DCMD, 184 MFI_CMD_ABORT, 185 MFI_CMD_SMP, 186 MFI_CMD_STP 187 } mfi_cmd_t; 188 189 /* Direct commands */ 190 typedef enum { 191 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC = 0x0100e100, 192 MFI_DCMD_CTRL_GETINFO = 0x01010000, 193 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 194 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 195 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 196 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 197 MFI_DCMD_PR_GET_STATUS = 0x01070100, 198 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 199 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 200 MFI_DCMD_PR_START = 0x01070400, 201 MFI_DCMD_PR_STOP = 0x01070500, 202 MFI_DCMD_TIME_SECS_GET = 0x01080201, 203 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 204 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 205 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 206 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 207 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 208 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 209 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 210 MFI_DCMD_PD_GET_LIST = 0x02010000, 211 MFI_DCMD_PD_LIST_QUERY = 0x02010100, 212 MFI_DCMD_PD_GET_INFO = 0x02020000, 213 MFI_DCMD_PD_STATE_SET = 0x02030100, 214 MFI_DCMD_PD_REBUILD_START = 0x02040100, 215 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 216 MFI_DCMD_PD_CLEAR_START = 0x02050100, 217 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 218 MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 219 MFI_DCMD_PD_LOCATE_START = 0x02070100, 220 MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 221 MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 222 MFI_DCMD_LD_SYNC = 0x0300e102, 223 MFI_DCMD_LD_GET_LIST = 0x03010000, 224 MFI_DCMD_LD_GET_INFO = 0x03020000, 225 MFI_DCMD_LD_GET_PROP = 0x03030000, 226 MFI_DCMD_LD_SET_PROP = 0x03040000, 227 MFI_DCMD_LD_INIT_START = 0x03060100, 228 MFI_DCMD_LD_DELETE = 0x03090000, 229 MFI_DCMD_CFG_READ = 0x04010000, 230 MFI_DCMD_CFG_ADD = 0x04020000, 231 MFI_DCMD_CFG_CLEAR = 0x04030000, 232 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 233 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 234 MFI_DCMD_CFG_FOREIGN_SCAN = 0x04060100, 235 MFI_DCMD_CFG_FOREIGN_DISPLAY = 0x04060200, 236 MFI_DCMD_CFG_FOREIGN_PREVIEW = 0x04060300, 237 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 238 MFI_DCMD_CFG_FOREIGN_CLEAR = 0x04060500, 239 MFI_DCMD_BBU_GET_STATUS = 0x05010000, 240 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 241 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 242 MFI_DCMD_CLUSTER = 0x08000000, 243 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 244 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 245 } mfi_dcmd_t; 246 247 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 248 #define MFI_FLUSHCACHE_CTRL 0x01 249 #define MFI_FLUSHCACHE_DISK 0x02 250 251 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 252 #define MFI_SHUTDOWN_SPINDOWN 0x01 253 254 /* 255 * MFI Frame flags 256 */ 257 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 258 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 259 #define MFI_FRAME_SGL32 0x0000 260 #define MFI_FRAME_SGL64 0x0002 261 #define MFI_FRAME_SENSE32 0x0000 262 #define MFI_FRAME_SENSE64 0x0004 263 #define MFI_FRAME_DIR_NONE 0x0000 264 #define MFI_FRAME_DIR_WRITE 0x0008 265 #define MFI_FRAME_DIR_READ 0x0010 266 #define MFI_FRAME_DIR_BOTH 0x0018 267 #define MFI_FRAME_IEEE_SGL 0x0020 268 269 /* ThunderBolt Specific */ 270 271 /* 272 * Pre-TB command size and TB command size. 273 * We will be checking it at the load time for the time being 274 */ 275 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 276 277 #define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 278 /* 279 * We are defining only 128 byte message to reduce memory move over head 280 * and also it will reduce the SRB extension size by 128byte compared with 281 * 256 message size 282 */ 283 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 284 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 285 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 286 #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 287 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 288 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 289 290 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 291 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 292 293 #define MR_INTERNAL_MFI_FRAMES_SMID 1 294 #define MR_CTRL_EVENT_WAIT_SMID 2 295 #define MR_INTERNAL_DRIVER_RESET_SMID 3 296 297 298 /* MFI Status codes */ 299 typedef enum { 300 MFI_STAT_OK = 0x00, 301 MFI_STAT_INVALID_CMD, 302 MFI_STAT_INVALID_DCMD, 303 MFI_STAT_INVALID_PARAMETER, 304 MFI_STAT_INVALID_SEQUENCE_NUMBER, 305 MFI_STAT_ABORT_NOT_POSSIBLE, 306 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 307 MFI_STAT_APP_IN_USE, 308 MFI_STAT_APP_NOT_INITIALIZED, 309 MFI_STAT_ARRAY_INDEX_INVALID, 310 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 311 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 312 MFI_STAT_DEVICE_NOT_FOUND, 313 MFI_STAT_DRIVE_TOO_SMALL, 314 MFI_STAT_FLASH_ALLOC_FAIL, 315 MFI_STAT_FLASH_BUSY, 316 MFI_STAT_FLASH_ERROR = 0x10, 317 MFI_STAT_FLASH_IMAGE_BAD, 318 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 319 MFI_STAT_FLASH_NOT_OPEN, 320 MFI_STAT_FLASH_NOT_STARTED, 321 MFI_STAT_FLUSH_FAILED, 322 MFI_STAT_HOST_CODE_NOT_FOUNT, 323 MFI_STAT_LD_CC_IN_PROGRESS, 324 MFI_STAT_LD_INIT_IN_PROGRESS, 325 MFI_STAT_LD_LBA_OUT_OF_RANGE, 326 MFI_STAT_LD_MAX_CONFIGURED, 327 MFI_STAT_LD_NOT_OPTIMAL, 328 MFI_STAT_LD_RBLD_IN_PROGRESS, 329 MFI_STAT_LD_RECON_IN_PROGRESS, 330 MFI_STAT_LD_WRONG_RAID_LEVEL, 331 MFI_STAT_MAX_SPARES_EXCEEDED, 332 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 333 MFI_STAT_MFC_HW_ERROR, 334 MFI_STAT_NO_HW_PRESENT, 335 MFI_STAT_NOT_FOUND, 336 MFI_STAT_NOT_IN_ENCL, 337 MFI_STAT_PD_CLEAR_IN_PROGRESS, 338 MFI_STAT_PD_TYPE_WRONG, 339 MFI_STAT_PR_DISABLED, 340 MFI_STAT_ROW_INDEX_INVALID, 341 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 342 MFI_STAT_SAS_CONFIG_INVALID_DATA, 343 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 344 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 345 MFI_STAT_SCSI_DONE_WITH_ERROR, 346 MFI_STAT_SCSI_IO_FAILED, 347 MFI_STAT_SCSI_RESERVATION_CONFLICT, 348 MFI_STAT_SHUTDOWN_FAILED = 0x30, 349 MFI_STAT_TIME_NOT_SET, 350 MFI_STAT_WRONG_STATE, 351 MFI_STAT_LD_OFFLINE, 352 MFI_STAT_PEER_NOTIFICATION_REJECTED, 353 MFI_STAT_PEER_NOTIFICATION_FAILED, 354 MFI_STAT_RESERVATION_IN_PROGRESS, 355 MFI_STAT_I2C_ERRORS_DETECTED, 356 MFI_STAT_PCI_ERRORS_DETECTED, 357 MFI_STAT_DIAG_FAILED, 358 MFI_STAT_BOOT_MSG_PENDING, 359 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 360 MFI_STAT_INVALID_STATUS = 0xFF 361 } mfi_status_t; 362 363 typedef enum { 364 MFI_EVT_CLASS_DEBUG = -2, 365 MFI_EVT_CLASS_PROGRESS = -1, 366 MFI_EVT_CLASS_INFO = 0, 367 MFI_EVT_CLASS_WARNING = 1, 368 MFI_EVT_CLASS_CRITICAL = 2, 369 MFI_EVT_CLASS_FATAL = 3, 370 MFI_EVT_CLASS_DEAD = 4 371 } mfi_evt_class_t; 372 373 typedef enum { 374 MFI_EVT_LOCALE_LD = 0x0001, 375 MFI_EVT_LOCALE_PD = 0x0002, 376 MFI_EVT_LOCALE_ENCL = 0x0004, 377 MFI_EVT_LOCALE_BBU = 0x0008, 378 MFI_EVT_LOCALE_SAS = 0x0010, 379 MFI_EVT_LOCALE_CTRL = 0x0020, 380 MFI_EVT_LOCALE_CONFIG = 0x0040, 381 MFI_EVT_LOCALE_CLUSTER = 0x0080, 382 MFI_EVT_LOCALE_ALL = 0xffff 383 } mfi_evt_locale_t; 384 385 typedef enum { 386 MR_EVT_ARGS_NONE = 0x00, 387 MR_EVT_ARGS_CDB_SENSE, 388 MR_EVT_ARGS_LD, 389 MR_EVT_ARGS_LD_COUNT, 390 MR_EVT_ARGS_LD_LBA, 391 MR_EVT_ARGS_LD_OWNER, 392 MR_EVT_ARGS_LD_LBA_PD_LBA, 393 MR_EVT_ARGS_LD_PROG, 394 MR_EVT_ARGS_LD_STATE, 395 MR_EVT_ARGS_LD_STRIP, 396 MR_EVT_ARGS_PD, 397 MR_EVT_ARGS_PD_ERR, 398 MR_EVT_ARGS_PD_LBA, 399 MR_EVT_ARGS_PD_LBA_LD, 400 MR_EVT_ARGS_PD_PROG, 401 MR_EVT_ARGS_PD_STATE, 402 MR_EVT_ARGS_PCI, 403 MR_EVT_ARGS_RATE, 404 MR_EVT_ARGS_STR, 405 MR_EVT_ARGS_TIME, 406 MR_EVT_ARGS_ECC 407 } mfi_evt_args; 408 409 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 410 #define MR_EVT_PD_REMOVED 0x0070 411 #define MR_EVT_PD_INSERTED 0x005b 412 413 typedef enum { 414 MR_LD_CACHE_WRITE_BACK = 0x01, 415 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 416 MR_LD_CACHE_READ_AHEAD = 0x04, 417 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 418 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 419 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 420 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 421 } mfi_ld_cache; 422 #define MR_LD_CACHE_MASK 0x7f 423 424 #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 425 #define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 426 #define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 427 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 428 #define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 429 #define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 430 #define MR_LD_CACHE_POLICY_IO_CACHED \ 431 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 432 #define MR_LD_CACHE_POLICY_IO_DIRECT 0 433 434 typedef enum { 435 MR_PD_CACHE_UNCHANGED = 0, 436 MR_PD_CACHE_ENABLE = 1, 437 MR_PD_CACHE_DISABLE = 2 438 } mfi_pd_cache; 439 440 typedef enum { 441 MR_PD_QUERY_TYPE_ALL = 0, 442 MR_PD_QUERY_TYPE_STATE = 1, 443 MR_PD_QUERY_TYPE_POWER_STATE = 2, 444 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 445 MR_PD_QUERY_TYPE_SPEED = 4, 446 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 447 } mfi_pd_query_type; 448 449 /* 450 * Other propertities and definitions 451 */ 452 #define MFI_MAX_PD_CHANNELS 2 453 #define MFI_MAX_LD_CHANNELS 2 454 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 455 #define MFI_MAX_CHANNEL_DEVS 128 456 #define MFI_DEFAULT_ID -1 457 #define MFI_MAX_LUN 8 458 #define MFI_MAX_LD 64 459 #define MFI_MAX_PD 256 460 461 #define MFI_FRAME_SIZE 64 462 #define MFI_MBOX_SIZE 12 463 464 /* Firmware flashing can take 40s */ 465 #define MFI_POLL_TIMEOUT_SECS 50 466 467 /* Allow for speedier math calculations */ 468 #define MFI_SECTOR_LEN 512 469 470 /* Scatter Gather elements */ 471 struct mfi_sg32 { 472 uint32_t addr; 473 uint32_t len; 474 } __packed; 475 476 struct mfi_sg64 { 477 uint64_t addr; 478 uint32_t len; 479 } __packed; 480 481 struct mfi_sg_skinny { 482 uint64_t addr; 483 uint32_t len; 484 uint32_t flag; 485 } __packed; 486 487 union mfi_sgl { 488 struct mfi_sg32 sg32[1]; 489 struct mfi_sg64 sg64[1]; 490 struct mfi_sg_skinny sg_skinny[1]; 491 } __packed; 492 493 /* Message frames. All messages have a common header */ 494 struct mfi_frame_header { 495 uint8_t cmd; 496 uint8_t sense_len; 497 uint8_t cmd_status; 498 uint8_t scsi_status; 499 uint8_t target_id; 500 uint8_t lun_id; 501 uint8_t cdb_len; 502 uint8_t sg_count; 503 uint32_t context; 504 /* 505 * pad0 is MSI Specific. Not used by Driver. Zero the value before 506 * sending the command to f/w. 507 */ 508 uint32_t pad0; 509 uint16_t flags; 510 #define MFI_FRAME_DATAOUT 0x08 511 #define MFI_FRAME_DATAIN 0x10 512 uint16_t timeout; 513 uint32_t data_len; 514 } __packed; 515 516 struct mfi_init_frame { 517 struct mfi_frame_header header; 518 uint32_t qinfo_new_addr_lo; 519 uint32_t qinfo_new_addr_hi; 520 uint32_t qinfo_old_addr_lo; 521 uint32_t qinfo_old_addr_hi; 522 // Start LSIP200113393 523 uint32_t driver_ver_lo; /*28h */ 524 uint32_t driver_ver_hi; /*2Ch */ 525 526 uint32_t reserved[4]; 527 // End LSIP200113393 528 } __packed; 529 530 /* 531 * Define MFI Address Context union. 532 */ 533 #ifdef MFI_ADDRESS_IS_uint64_t 534 typedef uint64_t MFI_ADDRESS; 535 #else 536 typedef union _MFI_ADDRESS { 537 struct { 538 uint32_t addressLow; 539 uint32_t addressHigh; 540 } u; 541 uint64_t address; 542 } MFI_ADDRESS, *PMFI_ADDRESS; 543 #endif 544 545 #define MFI_IO_FRAME_SIZE 40 546 struct mfi_io_frame { 547 struct mfi_frame_header header; 548 uint32_t sense_addr_lo; 549 uint32_t sense_addr_hi; 550 uint32_t lba_lo; 551 uint32_t lba_hi; 552 union mfi_sgl sgl; 553 } __packed; 554 555 #define MFI_PASS_FRAME_SIZE 48 556 struct mfi_pass_frame { 557 struct mfi_frame_header header; 558 uint32_t sense_addr_lo; 559 uint32_t sense_addr_hi; 560 uint8_t cdb[16]; 561 union mfi_sgl sgl; 562 } __packed; 563 564 #define MFI_DCMD_FRAME_SIZE 40 565 struct mfi_dcmd_frame { 566 struct mfi_frame_header header; 567 uint32_t opcode; 568 uint8_t mbox[MFI_MBOX_SIZE]; 569 union mfi_sgl sgl; 570 } __packed; 571 572 struct mfi_abort_frame { 573 struct mfi_frame_header header; 574 uint32_t abort_context; 575 /* pad is changed to reserved.*/ 576 uint32_t reserved0; 577 uint32_t abort_mfi_addr_lo; 578 uint32_t abort_mfi_addr_hi; 579 uint32_t reserved1[6]; 580 } __packed; 581 582 struct mfi_smp_frame { 583 struct mfi_frame_header header; 584 uint64_t sas_addr; 585 union { 586 struct mfi_sg32 sg32[2]; 587 struct mfi_sg64 sg64[2]; 588 } sgl; 589 } __packed; 590 591 struct mfi_stp_frame { 592 struct mfi_frame_header header; 593 uint16_t fis[10]; 594 uint32_t stp_flags; 595 union { 596 struct mfi_sg32 sg32[2]; 597 struct mfi_sg64 sg64[2]; 598 } sgl; 599 } __packed; 600 601 union mfi_frame { 602 struct mfi_frame_header header; 603 struct mfi_init_frame init; 604 /* ThunderBolt Initialization */ 605 struct mfi_io_frame io; 606 struct mfi_pass_frame pass; 607 struct mfi_dcmd_frame dcmd; 608 struct mfi_abort_frame abort; 609 struct mfi_smp_frame smp; 610 struct mfi_stp_frame stp; 611 uint8_t bytes[MFI_FRAME_SIZE]; 612 }; 613 614 #define MFI_SENSE_LEN 128 615 struct mfi_sense { 616 uint8_t data[MFI_SENSE_LEN]; 617 }; 618 619 /* The queue init structure that is passed with the init message */ 620 struct mfi_init_qinfo { 621 uint32_t flags; 622 uint32_t rq_entries; 623 uint32_t rq_addr_lo; 624 uint32_t rq_addr_hi; 625 uint32_t pi_addr_lo; 626 uint32_t pi_addr_hi; 627 uint32_t ci_addr_lo; 628 uint32_t ci_addr_hi; 629 } __packed; 630 631 /* SAS (?) controller properties, part of mfi_ctrl_info */ 632 struct mfi_ctrl_props { 633 uint16_t seq_num; 634 uint16_t pred_fail_poll_interval; 635 uint16_t intr_throttle_cnt; 636 uint16_t intr_throttle_timeout; 637 uint8_t rebuild_rate; 638 uint8_t patrol_read_rate; 639 uint8_t bgi_rate; 640 uint8_t cc_rate; 641 uint8_t recon_rate; 642 uint8_t cache_flush_interval; 643 uint8_t spinup_drv_cnt; 644 uint8_t spinup_delay; 645 uint8_t cluster_enable; 646 uint8_t coercion_mode; 647 uint8_t alarm_enable; 648 uint8_t disable_auto_rebuild; 649 uint8_t disable_battery_warn; 650 uint8_t ecc_bucket_size; 651 uint16_t ecc_bucket_leak_rate; 652 uint8_t restore_hotspare_on_insertion; 653 uint8_t expose_encl_devices; 654 uint8_t maintainPdFailHistory; 655 uint8_t disallowHostRequestReordering; 656 /* set TRUE to abort CC on detecting an inconsistency */ 657 uint8_t abortCCOnError; 658 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 659 uint8_t loadBalanceMode; 660 /* 661 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 662 * h/w mechansim like GPIO pins 663 * 1 - disable auto detect SGPIO, 664 * 2 - disable i2c SEP auto detect 665 * 3 - disable both auto detect 666 */ 667 uint8_t disableAutoDetectBackplane; 668 /* 669 * % of source LD to be reserved for a VDs snapshot in snapshot 670 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 671 */ 672 uint8_t snapVDSpace; 673 674 /* 675 * Add properties that can be controlled by a bit in the following 676 * structure. 677 */ 678 struct { 679 /* set TRUE to disable copyBack (0=copback enabled) */ 680 uint32_t copyBackDisabled :1; 681 uint32_t SMARTerEnabled :1; 682 uint32_t prCorrectUnconfiguredAreas :1; 683 uint32_t useFdeOnly :1; 684 uint32_t disableNCQ :1; 685 uint32_t SSDSMARTerEnabled :1; 686 uint32_t SSDPatrolReadEnabled :1; 687 uint32_t enableSpinDownUnconfigured :1; 688 uint32_t autoEnhancedImport :1; 689 uint32_t enableSecretKeyControl :1; 690 uint32_t disableOnlineCtrlReset :1; 691 uint32_t allowBootWithPinnedCache :1; 692 uint32_t disableSpinDownHS :1; 693 uint32_t enableJBOD :1; 694 uint32_t reserved :18; 695 } OnOffProperties; 696 /* 697 * % of source LD to be reserved for auto snapshot in snapshot 698 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 699 */ 700 uint8_t autoSnapVDSpace; 701 /* 702 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 703 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 704 */ 705 uint8_t viewSpace; 706 /* # of idle minutes before device is spun down (0=use FW defaults) */ 707 uint16_t spinDownTime; 708 uint8_t reserved[24]; 709 } __packed; 710 711 /* PCI information about the card. */ 712 struct mfi_info_pci { 713 uint16_t vendor; 714 uint16_t device; 715 uint16_t subvendor; 716 uint16_t subdevice; 717 uint8_t reserved[24]; 718 } __packed; 719 720 /* Host (front end) interface information */ 721 struct mfi_info_host { 722 uint8_t type; 723 #define MFI_INFO_HOST_PCIX 0x01 724 #define MFI_INFO_HOST_PCIE 0x02 725 #define MFI_INFO_HOST_ISCSI 0x04 726 #define MFI_INFO_HOST_SAS3G 0x08 727 uint8_t reserved[6]; 728 uint8_t port_count; 729 uint64_t port_addr[8]; 730 } __packed; 731 732 /* Device (back end) interface information */ 733 struct mfi_info_device { 734 uint8_t type; 735 #define MFI_INFO_DEV_SPI 0x01 736 #define MFI_INFO_DEV_SAS3G 0x02 737 #define MFI_INFO_DEV_SATA1 0x04 738 #define MFI_INFO_DEV_SATA3G 0x08 739 uint8_t reserved[6]; 740 uint8_t port_count; 741 uint64_t port_addr[8]; 742 } __packed; 743 744 /* Firmware component information */ 745 struct mfi_info_component { 746 char name[8]; 747 char version[32]; 748 char build_date[16]; 749 char build_time[16]; 750 } __packed; 751 752 /* Controller default settings */ 753 struct mfi_defaults { 754 uint64_t sas_addr; 755 uint8_t phy_polarity; 756 uint8_t background_rate; 757 uint8_t stripe_size; 758 uint8_t flush_time; 759 uint8_t write_back; 760 uint8_t read_ahead; 761 uint8_t cache_when_bbu_bad; 762 uint8_t cached_io; 763 uint8_t smart_mode; 764 uint8_t alarm_disable; 765 uint8_t coercion; 766 uint8_t zrc_config; 767 uint8_t dirty_led_shows_drive_activity; 768 uint8_t bios_continue_on_error; 769 uint8_t spindown_mode; 770 uint8_t allowed_device_types; 771 uint8_t allow_mix_in_enclosure; 772 uint8_t allow_mix_in_ld; 773 uint8_t allow_sata_in_cluster; 774 uint8_t max_chained_enclosures; 775 uint8_t disable_ctrl_r; 776 uint8_t enabel_web_bios; 777 uint8_t phy_polarity_split; 778 uint8_t direct_pd_mapping; 779 uint8_t bios_enumerate_lds; 780 uint8_t restored_hot_spare_on_insertion; 781 uint8_t expose_enclosure_devices; 782 uint8_t maintain_pd_fail_history; 783 uint8_t resv[28]; 784 } __packed; 785 786 /* Controller default settings */ 787 struct mfi_bios_data { 788 uint16_t boot_target_id; 789 uint8_t do_not_int_13; 790 uint8_t continue_on_error; 791 uint8_t verbose; 792 uint8_t geometry; 793 uint8_t expose_all_drives; 794 uint8_t reserved[56]; 795 uint8_t check_sum; 796 } __packed; 797 798 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 799 struct mfi_ctrl_info { 800 struct mfi_info_pci pci; 801 struct mfi_info_host host; 802 struct mfi_info_device device; 803 804 /* Firmware components that are present and active. */ 805 uint32_t image_check_word; 806 uint32_t image_component_count; 807 struct mfi_info_component image_component[8]; 808 809 /* Firmware components that have been flashed but are inactive */ 810 uint32_t pending_image_component_count; 811 struct mfi_info_component pending_image_component[8]; 812 813 uint8_t max_arms; 814 uint8_t max_spans; 815 uint8_t max_arrays; 816 uint8_t max_lds; 817 char product_name[80]; 818 char serial_number[32]; 819 uint32_t hw_present; 820 #define MFI_INFO_HW_BBU 0x01 821 #define MFI_INFO_HW_ALARM 0x02 822 #define MFI_INFO_HW_NVRAM 0x04 823 #define MFI_INFO_HW_UART 0x08 824 uint32_t current_fw_time; 825 uint16_t max_cmds; 826 uint16_t max_sg_elements; 827 uint32_t max_request_size; 828 uint16_t lds_present; 829 uint16_t lds_degraded; 830 uint16_t lds_offline; 831 uint16_t pd_present; 832 uint16_t pd_disks_present; 833 uint16_t pd_disks_pred_failure; 834 uint16_t pd_disks_failed; 835 uint16_t nvram_size; 836 uint16_t memory_size; 837 uint16_t flash_size; 838 uint16_t ram_correctable_errors; 839 uint16_t ram_uncorrectable_errors; 840 uint8_t cluster_allowed; 841 uint8_t cluster_active; 842 uint16_t max_strips_per_io; 843 844 uint32_t raid_levels; 845 #define MFI_INFO_RAID_0 0x01 846 #define MFI_INFO_RAID_1 0x02 847 #define MFI_INFO_RAID_5 0x04 848 #define MFI_INFO_RAID_1E 0x08 849 #define MFI_INFO_RAID_6 0x10 850 851 uint32_t adapter_ops; 852 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 853 #define MFI_INFO_AOPS_CC_RATE 0x0002 854 #define MFI_INFO_AOPS_BGI_RATE 0x0004 855 #define MFI_INFO_AOPS_RECON_RATE 0x0008 856 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 857 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 858 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 859 #define MFI_INFO_AOPS_BBU 0x0080 860 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 861 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 862 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 863 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 864 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 865 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 866 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 867 868 uint32_t ld_ops; 869 #define MFI_INFO_LDOPS_READ_POLICY 0x01 870 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 871 #define MFI_INFO_LDOPS_IO_POLICY 0x04 872 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 873 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 874 875 struct { 876 uint8_t min; 877 uint8_t max; 878 uint8_t reserved[2]; 879 } __packed stripe_sz_ops; 880 881 uint32_t pd_ops; 882 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 883 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 884 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 885 886 uint32_t pd_mix_support; 887 #define MFI_INFO_PDMIX_SAS 0x01 888 #define MFI_INFO_PDMIX_SATA 0x02 889 #define MFI_INFO_PDMIX_ENCL 0x04 890 #define MFI_INFO_PDMIX_LD 0x08 891 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 892 893 uint8_t ecc_bucket_count; 894 uint8_t reserved2[11]; 895 struct mfi_ctrl_props properties; 896 char package_version[0x60]; 897 uint8_t pad[0x800 - 0x6a0]; 898 } __packed; 899 900 /* keep track of an event. */ 901 union mfi_evt { 902 struct { 903 uint16_t locale; 904 uint8_t reserved; 905 int8_t evt_class; 906 } members; 907 uint32_t word; 908 } __packed; 909 910 /* event log state. */ 911 struct mfi_evt_log_state { 912 uint32_t newest_seq_num; 913 uint32_t oldest_seq_num; 914 uint32_t clear_seq_num; 915 uint32_t shutdown_seq_num; 916 uint32_t boot_seq_num; 917 } __packed; 918 919 struct mfi_progress { 920 uint16_t progress; 921 uint16_t elapsed_seconds; 922 } __packed; 923 924 struct mfi_evt_ld { 925 uint16_t target_id; 926 uint8_t ld_index; 927 uint8_t reserved; 928 } __packed; 929 930 struct mfi_evt_pd { 931 uint16_t device_id; 932 uint8_t enclosure_index; 933 uint8_t slot_number; 934 } __packed; 935 936 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 937 struct mfi_evt_detail { 938 uint32_t seq; 939 uint32_t time; 940 uint32_t code; 941 union mfi_evt evt_class; 942 uint8_t arg_type; 943 uint8_t reserved1[15]; 944 945 union { 946 struct { 947 struct mfi_evt_pd pd; 948 uint8_t cdb_len; 949 uint8_t sense_len; 950 uint8_t reserved[2]; 951 uint8_t cdb[16]; 952 uint8_t sense[64]; 953 } cdb_sense; 954 955 struct mfi_evt_ld ld; 956 957 struct { 958 struct mfi_evt_ld ld; 959 uint64_t count; 960 } ld_count; 961 962 struct { 963 uint64_t lba; 964 struct mfi_evt_ld ld; 965 } ld_lba; 966 967 struct { 968 struct mfi_evt_ld ld; 969 uint32_t pre_owner; 970 uint32_t new_owner; 971 } ld_owner; 972 973 struct { 974 uint64_t ld_lba; 975 uint64_t pd_lba; 976 struct mfi_evt_ld ld; 977 struct mfi_evt_pd pd; 978 } ld_lba_pd_lba; 979 980 struct { 981 struct mfi_evt_ld ld; 982 struct mfi_progress prog; 983 } ld_prog; 984 985 struct { 986 struct mfi_evt_ld ld; 987 uint32_t prev_state; 988 uint32_t new_state; 989 } ld_state; 990 991 struct { 992 uint64_t strip; 993 struct mfi_evt_ld ld; 994 } ld_strip; 995 996 struct mfi_evt_pd pd; 997 998 struct { 999 struct mfi_evt_pd pd; 1000 uint32_t err; 1001 } pd_err; 1002 1003 struct { 1004 uint64_t lba; 1005 struct mfi_evt_pd pd; 1006 } pd_lba; 1007 1008 struct { 1009 uint64_t lba; 1010 struct mfi_evt_pd pd; 1011 struct mfi_evt_ld ld; 1012 } pd_lba_ld; 1013 1014 struct { 1015 struct mfi_evt_pd pd; 1016 struct mfi_progress prog; 1017 } pd_prog; 1018 1019 struct { 1020 struct mfi_evt_pd ld; 1021 uint32_t prev_state; 1022 uint32_t new_state; 1023 } pd_state; 1024 1025 struct { 1026 uint16_t venderId; 1027 uint16_t deviceId; 1028 uint16_t subVenderId; 1029 uint16_t subDeviceId; 1030 } pci; 1031 1032 uint32_t rate; 1033 1034 char str[96]; 1035 1036 struct { 1037 uint32_t rtc; 1038 uint16_t elapsedSeconds; 1039 } time; 1040 1041 struct { 1042 uint32_t ecar; 1043 uint32_t elog; 1044 char str[64]; 1045 } ecc; 1046 1047 uint8_t b[96]; 1048 uint16_t s[48]; 1049 uint32_t w[24]; 1050 uint64_t d[12]; 1051 } args; 1052 1053 char description[128]; 1054 } __packed; 1055 1056 struct mfi_evt_list { 1057 uint32_t count; 1058 uint32_t reserved; 1059 struct mfi_evt_detail event[1]; 1060 } __packed; 1061 1062 union mfi_pd_ref { 1063 struct { 1064 uint16_t device_id; 1065 uint16_t seq_num; 1066 } v; 1067 uint32_t ref; 1068 } __packed; 1069 1070 union mfi_pd_ddf_type { 1071 struct { 1072 union { 1073 struct { 1074 uint16_t forced_pd_guid : 1; 1075 uint16_t in_vd : 1; 1076 uint16_t is_global_spare : 1; 1077 uint16_t is_spare : 1; 1078 uint16_t is_foreign : 1; 1079 uint16_t reserved : 7; 1080 uint16_t intf : 4; 1081 } pd_type; 1082 uint16_t type; 1083 } v; 1084 uint16_t reserved; 1085 } ddf; 1086 struct { 1087 uint32_t reserved; 1088 } non_disk; 1089 uint32_t type; 1090 } __packed; 1091 1092 struct mfi_pd_progress { 1093 uint32_t active; 1094 #define MFI_PD_PROGRESS_REBUILD (1<<0) 1095 #define MFI_PD_PROGRESS_PATROL (1<<1) 1096 #define MFI_PD_PROGRESS_CLEAR (1<<2) 1097 struct mfi_progress rbld; 1098 struct mfi_progress patrol; 1099 struct mfi_progress clear; 1100 struct mfi_progress reserved[4]; 1101 } __packed; 1102 1103 struct mfi_pd_info { 1104 union mfi_pd_ref ref; 1105 uint8_t inquiry_data[96]; 1106 uint8_t vpd_page83[64]; 1107 uint8_t not_supported; 1108 uint8_t scsi_dev_type; 1109 uint8_t connected_port_bitmap; 1110 uint8_t device_speed; 1111 uint32_t media_err_count; 1112 uint32_t other_err_count; 1113 uint32_t pred_fail_count; 1114 uint32_t last_pred_fail_event_seq_num; 1115 uint16_t fw_state; /* MFI_PD_STATE_* */ 1116 uint8_t disabled_for_removal; 1117 uint8_t link_speed; 1118 union mfi_pd_ddf_type state; 1119 struct { 1120 uint8_t count; 1121 uint8_t is_path_broken; 1122 uint8_t reserved[6]; 1123 uint64_t sas_addr[4]; 1124 } path_info; 1125 uint64_t raw_size; 1126 uint64_t non_coerced_size; 1127 uint64_t coerced_size; 1128 uint16_t encl_device_id; 1129 uint8_t encl_index; 1130 uint8_t slot_number; 1131 struct mfi_pd_progress prog_info; 1132 uint8_t bad_block_table_full; 1133 uint8_t unusable_in_current_config; 1134 uint8_t vpd_page83_ext[64]; 1135 uint8_t reserved[512-358]; 1136 } __packed; 1137 1138 struct mfi_pd_address { 1139 uint16_t device_id; 1140 uint16_t encl_device_id; 1141 uint8_t encl_index; 1142 uint8_t slot_number; 1143 uint8_t scsi_dev_type; /* 0 = disk */ 1144 uint8_t connect_port_bitmap; 1145 uint64_t sas_addr[2]; 1146 } __packed; 1147 1148 #define MAX_SYS_PDS 240 1149 struct mfi_pd_list { 1150 uint32_t size; 1151 uint32_t count; 1152 struct mfi_pd_address addr[MAX_SYS_PDS]; 1153 } __packed; 1154 1155 enum mfi_pd_state { 1156 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1157 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1158 MFI_PD_STATE_HOT_SPARE = 0x02, 1159 MFI_PD_STATE_OFFLINE = 0x10, 1160 MFI_PD_STATE_FAILED = 0x11, 1161 MFI_PD_STATE_REBUILD = 0x14, 1162 MFI_PD_STATE_ONLINE = 0x18, 1163 MFI_PD_STATE_COPYBACK = 0x20, 1164 MFI_PD_STATE_SYSTEM = 0x40 1165 }; 1166 1167 union mfi_ld_ref { 1168 struct { 1169 uint8_t target_id; 1170 uint8_t reserved; 1171 uint16_t seq; 1172 } v; 1173 uint32_t ref; 1174 } __packed; 1175 1176 struct mfi_ld_list { 1177 uint32_t ld_count; 1178 uint32_t reserved1; 1179 struct { 1180 union mfi_ld_ref ld; 1181 uint8_t state; 1182 uint8_t reserved2[3]; 1183 uint64_t size; 1184 } ld_list[MFI_MAX_LD]; 1185 } __packed; 1186 1187 enum mfi_ld_access { 1188 MFI_LD_ACCESS_RW = 0, 1189 MFI_LD_ACCSSS_RO = 2, 1190 MFI_LD_ACCESS_BLOCKED = 3, 1191 }; 1192 #define MFI_LD_ACCESS_MASK 3 1193 1194 enum mfi_ld_state { 1195 MFI_LD_STATE_OFFLINE = 0, 1196 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1197 MFI_LD_STATE_DEGRADED = 2, 1198 MFI_LD_STATE_OPTIMAL = 3 1199 }; 1200 1201 struct mfi_ld_props { 1202 union mfi_ld_ref ld; 1203 char name[16]; 1204 uint8_t default_cache_policy; 1205 uint8_t access_policy; 1206 uint8_t disk_cache_policy; 1207 uint8_t current_cache_policy; 1208 uint8_t no_bgi; 1209 uint8_t reserved[7]; 1210 } __packed; 1211 1212 struct mfi_ld_params { 1213 uint8_t primary_raid_level; 1214 uint8_t raid_level_qualifier; 1215 uint8_t secondary_raid_level; 1216 uint8_t stripe_size; 1217 uint8_t num_drives; 1218 uint8_t span_depth; 1219 uint8_t state; 1220 uint8_t init_state; 1221 #define MFI_LD_PARAMS_INIT_NO 0 1222 #define MFI_LD_PARAMS_INIT_QUICK 1 1223 #define MFI_LD_PARAMS_INIT_FULL 2 1224 uint8_t is_consistent; 1225 uint8_t reserved1[6]; 1226 uint8_t isSSCD; 1227 uint8_t reserved2[16]; 1228 } __packed; 1229 1230 struct mfi_ld_progress { 1231 uint32_t active; 1232 #define MFI_LD_PROGRESS_CC (1<<0) 1233 #define MFI_LD_PROGRESS_BGI (1<<1) 1234 #define MFI_LD_PROGRESS_FGI (1<<2) 1235 #define MFI_LD_PROGRESS_RECON (1<<3) 1236 struct mfi_progress cc; 1237 struct mfi_progress bgi; 1238 struct mfi_progress fgi; 1239 struct mfi_progress recon; 1240 struct mfi_progress reserved[4]; 1241 } __packed; 1242 1243 struct mfi_span { 1244 uint64_t start_block; 1245 uint64_t num_blocks; 1246 uint16_t array_ref; 1247 uint8_t reserved[6]; 1248 } __packed; 1249 1250 #define MFI_MAX_SPAN_DEPTH 8 1251 struct mfi_ld_config { 1252 struct mfi_ld_props properties; 1253 struct mfi_ld_params params; 1254 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1255 } __packed; 1256 1257 struct mfi_ld_info { 1258 struct mfi_ld_config ld_config; 1259 uint64_t size; 1260 struct mfi_ld_progress progress; 1261 uint16_t cluster_owner; 1262 uint8_t reconstruct_active; 1263 uint8_t reserved1[1]; 1264 uint8_t vpd_page83[64]; 1265 uint8_t reserved2[16]; 1266 } __packed; 1267 1268 #define MAX_ARRAYS 128 1269 struct mfi_spare { 1270 union mfi_pd_ref ref; 1271 uint8_t spare_type; 1272 #define MFI_SPARE_DEDICATED (1 << 0) 1273 #define MFI_SPARE_REVERTIBLE (1 << 1) 1274 #define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1275 uint8_t reserved[2]; 1276 uint8_t array_count; 1277 uint16_t array_ref[MAX_ARRAYS]; 1278 } __packed; 1279 1280 struct mfi_array { 1281 uint64_t size; 1282 uint8_t num_drives; 1283 uint8_t reserved; 1284 uint16_t array_ref; 1285 uint8_t pad[20]; 1286 struct { 1287 union mfi_pd_ref ref; /* 0xffff == missing drive */ 1288 uint16_t fw_state; /* MFI_PD_STATE_* */ 1289 struct { 1290 uint8_t pd; 1291 uint8_t slot; 1292 } encl; 1293 } pd[0]; 1294 } __packed; 1295 1296 struct mfi_config_data { 1297 uint32_t size; 1298 uint16_t array_count; 1299 uint16_t array_size; 1300 uint16_t log_drv_count; 1301 uint16_t log_drv_size; 1302 uint16_t spares_count; 1303 uint16_t spares_size; 1304 uint8_t reserved[16]; 1305 struct mfi_array array[0]; 1306 struct mfi_ld_config ld[0]; 1307 struct mfi_spare spare[0]; 1308 } __packed; 1309 1310 struct mfi_bbu_capacity_info { 1311 uint16_t relative_charge; 1312 uint16_t absolute_charge; 1313 uint16_t remaining_capacity; 1314 uint16_t full_charge_capacity; 1315 uint16_t run_time_to_empty; 1316 uint16_t average_time_to_empty; 1317 uint16_t average_time_to_full; 1318 uint16_t cycle_count; 1319 uint16_t max_error; 1320 uint16_t remaining_capacity_alarm; 1321 uint16_t remaining_time_alarm; 1322 uint8_t reserved[26]; 1323 } __packed; 1324 1325 struct mfi_bbu_design_info { 1326 uint32_t mfg_date; 1327 uint16_t design_capacity; 1328 uint16_t design_voltage; 1329 uint16_t spec_info; 1330 uint16_t serial_number; 1331 uint16_t pack_stat_config; 1332 uint8_t mfg_name[12]; 1333 uint8_t device_name[8]; 1334 uint8_t device_chemistry[8]; 1335 uint8_t mfg_data[8]; 1336 uint8_t reserved[17]; 1337 } __packed; 1338 1339 struct mfi_ibbu_state { 1340 uint16_t gas_guage_status; 1341 uint16_t relative_charge; 1342 uint16_t charger_system_state; 1343 uint16_t charger_system_ctrl; 1344 uint16_t charging_current; 1345 uint16_t absolute_charge; 1346 uint16_t max_error; 1347 uint8_t reserved[18]; 1348 } __packed; 1349 1350 struct mfi_bbu_state { 1351 uint16_t gas_guage_status; 1352 uint16_t relative_charge; 1353 uint16_t charger_status; 1354 uint16_t remaining_capacity; 1355 uint16_t full_charge_capacity; 1356 uint8_t is_SOH_good; 1357 uint8_t reserved[21]; 1358 } __packed; 1359 1360 union mfi_bbu_status_detail { 1361 struct mfi_ibbu_state ibbu; 1362 struct mfi_bbu_state bbu; 1363 }; 1364 1365 struct mfi_bbu_status { 1366 uint8_t battery_type; 1367 #define MFI_BBU_TYPE_NONE 0 1368 #define MFI_BBU_TYPE_IBBU 1 1369 #define MFI_BBU_TYPE_BBU 2 1370 uint8_t reserved; 1371 uint16_t voltage; 1372 int16_t current; 1373 uint16_t temperature; 1374 uint32_t fw_status; 1375 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1376 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1377 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1378 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 0) 1379 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 0) 1380 uint8_t pad[20]; 1381 union mfi_bbu_status_detail detail; 1382 } __packed; 1383 1384 enum mfi_pr_state { 1385 MFI_PR_STATE_STOPPED = 0, 1386 MFI_PR_STATE_READY = 1, 1387 MFI_PR_STATE_ACTIVE = 2, 1388 MFI_PR_STATE_ABORTED = 0xff 1389 }; 1390 1391 struct mfi_pr_status { 1392 uint32_t num_iteration; 1393 uint8_t state; 1394 uint8_t num_pd_done; 1395 uint8_t reserved[10]; 1396 }; 1397 1398 enum mfi_pr_opmode { 1399 MFI_PR_OPMODE_AUTO = 0, 1400 MFI_PR_OPMODE_MANUAL = 1, 1401 MFI_PR_OPMODE_DISABLED = 2 1402 }; 1403 1404 struct mfi_pr_properties { 1405 uint8_t op_mode; 1406 uint8_t max_pd; 1407 uint8_t reserved; 1408 uint8_t exclude_ld_count; 1409 uint16_t excluded_ld[MFI_MAX_LD]; 1410 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1411 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1412 uint32_t next_exec; 1413 uint32_t exec_freq; 1414 uint32_t clear_freq; 1415 }; 1416 1417 /* ThunderBolt support */ 1418 1419 /* 1420 * Raid Context structure which describes MegaRAID specific IO Paramenters 1421 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1422 */ 1423 typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1424 uint16_t resvd0; /* 0x00 - 0x01 */ 1425 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1426 uint8_t regLockFlags; 1427 uint8_t armId; 1428 uint16_t TargetID; /* 0x06 - 0x07 */ 1429 1430 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1431 1432 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1433 1434 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1435 uint8_t exStatus; /* 0x16 */ 1436 uint8_t Status; /* 0x17 status */ 1437 1438 uint8_t RAIDFlags; /* 0x18 */ 1439 uint8_t numSGE; /* 0x19 numSge */ 1440 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1441 uint8_t spanArm; /* 0x1C */ 1442 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1443 } MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1444 1445 /*** DJA *****/ 1446 1447 /***************************************************************************** 1448 * 1449 * Message Functions 1450 * 1451 *****************************************************************************/ 1452 1453 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1454 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1455 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1456 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1457 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1458 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1459 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1460 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1461 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1462 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1463 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1464 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1465 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1466 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1467 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1468 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1469 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1470 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1471 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1472 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1473 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1474 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1475 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1476 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1477 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1478 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1479 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1480 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1481 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1482 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1483 1484 /* Doorbell functions */ 1485 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1486 #define MPI2_FUNCTION_HANDSHAKE (0x42) 1487 1488 /***************************************************************************** 1489 * 1490 * MPI Version Definitions 1491 * 1492 *****************************************************************************/ 1493 1494 #define MPI2_VERSION_MAJOR (0x02) 1495 #define MPI2_VERSION_MINOR (0x00) 1496 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1497 #define MPI2_VERSION_MAJOR_SHIFT (8) 1498 #define MPI2_VERSION_MINOR_MASK (0x00FF) 1499 #define MPI2_VERSION_MINOR_SHIFT (0) 1500 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1501 MPI2_VERSION_MINOR) 1502 1503 #define MPI2_VERSION_02_00 (0x0200) 1504 1505 /* versioning for this MPI header set */ 1506 #define MPI2_HEADER_VERSION_UNIT (0x10) 1507 #define MPI2_HEADER_VERSION_DEV (0x00) 1508 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1509 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1510 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1511 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1512 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1513 MPI2_HEADER_VERSION_DEV) 1514 1515 1516 /* IOCInit Request message */ 1517 struct MPI2_IOC_INIT_REQUEST { 1518 uint8_t WhoInit; /* 0x00 */ 1519 uint8_t Reserved1; /* 0x01 */ 1520 uint8_t ChainOffset; /* 0x02 */ 1521 uint8_t Function; /* 0x03 */ 1522 uint16_t Reserved2; /* 0x04 */ 1523 uint8_t Reserved3; /* 0x06 */ 1524 uint8_t MsgFlags; /* 0x07 */ 1525 uint8_t VP_ID; /* 0x08 */ 1526 uint8_t VF_ID; /* 0x09 */ 1527 uint16_t Reserved4; /* 0x0A */ 1528 uint16_t MsgVersion; /* 0x0C */ 1529 uint16_t HeaderVersion; /* 0x0E */ 1530 uint32_t Reserved5; /* 0x10 */ 1531 uint16_t Reserved6; /* 0x14 */ 1532 uint8_t Reserved7; /* 0x16 */ 1533 uint8_t HostMSIxVectors; /* 0x17 */ 1534 uint16_t Reserved8; /* 0x18 */ 1535 uint16_t SystemRequestFrameSize; /* 0x1A */ 1536 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1537 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1538 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1539 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1540 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1541 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1542 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1543 uint64_t TimeStamp; /* 0x40 */ 1544 }; 1545 1546 /* WhoInit values */ 1547 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1548 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1549 #define MPI2_WHOINIT_ROM_BIOS (0x02) 1550 #define MPI2_WHOINIT_PCI_PEER (0x03) 1551 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1552 #define MPI2_WHOINIT_MANUFACTURER (0x05) 1553 1554 struct MPI2_SGE_CHAIN_UNION { 1555 uint16_t Length; 1556 uint8_t NextChainOffset; 1557 uint8_t Flags; 1558 union { 1559 uint32_t Address32; 1560 uint64_t Address64; 1561 } u; 1562 }; 1563 1564 struct MPI2_IEEE_SGE_SIMPLE32 { 1565 uint32_t Address; 1566 uint32_t FlagsLength; 1567 }; 1568 1569 struct MPI2_IEEE_SGE_SIMPLE64 { 1570 uint64_t Address; 1571 uint32_t Length; 1572 uint16_t Reserved1; 1573 uint8_t Reserved2; 1574 uint8_t Flags; 1575 }; 1576 1577 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1578 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1579 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1580 } MPI2_IEEE_SGE_SIMPLE_UNION; 1581 1582 typedef struct _MPI2_SGE_SIMPLE_UNION { 1583 uint32_t FlagsLength; 1584 union { 1585 uint32_t Address32; 1586 uint64_t Address64; 1587 } u; 1588 } MPI2_SGE_SIMPLE_UNION; 1589 1590 /**************************************************************************** 1591 * IEEE SGE field definitions and masks 1592 ****************************************************************************/ 1593 1594 /* Flags field bit definitions */ 1595 1596 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1597 1598 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1599 1600 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1601 1602 /* Element Type */ 1603 1604 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1605 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1606 1607 /* Data Location Address Space */ 1608 1609 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1610 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1611 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1612 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1613 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1614 1615 /* Address Size */ 1616 1617 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1618 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1619 1620 /*******************/ 1621 /* SCSI IO Control bits */ 1622 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1623 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1624 1625 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1626 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1627 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1628 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1629 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1630 1631 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1632 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1633 1634 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1635 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1636 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1637 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1638 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1639 1640 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1641 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1642 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1643 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1644 1645 /*******************/ 1646 1647 typedef struct { 1648 uint8_t CDB[20]; /* 0x00 */ 1649 uint32_t PrimaryReferenceTag; /* 0x14 */ 1650 uint16_t PrimaryApplicationTag; /* 0x18 */ 1651 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1652 uint32_t TransferLength; /* 0x1C */ 1653 } MPI2_SCSI_IO_CDB_EEDP32; 1654 1655 1656 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1657 struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1658 struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1659 } MPI2_IEEE_SGE_CHAIN_UNION; 1660 1661 typedef union _MPI2_SIMPLE_SGE_UNION { 1662 MPI2_SGE_SIMPLE_UNION MpiSimple; 1663 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1664 } MPI2_SIMPLE_SGE_UNION; 1665 1666 typedef union _MPI2_SGE_IO_UNION { 1667 MPI2_SGE_SIMPLE_UNION MpiSimple; 1668 struct MPI2_SGE_CHAIN_UNION MpiChain; 1669 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1670 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1671 } MPI2_SGE_IO_UNION; 1672 1673 typedef union { 1674 uint8_t CDB32[32]; 1675 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1676 MPI2_SGE_SIMPLE_UNION SGE; 1677 } MPI2_SCSI_IO_CDB_UNION; 1678 1679 1680 /* MPI 2.5 SGLs */ 1681 1682 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1683 1684 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1685 uint64_t Address; 1686 uint32_t Length; 1687 uint16_t Reserved1; 1688 uint8_t NextChainOffset; 1689 uint8_t Flags; 1690 } MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1691 1692 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1693 1694 1695 /********/ 1696 1697 /* 1698 * RAID SCSI IO Request Message 1699 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1700 */ 1701 struct mfi_mpi2_request_raid_scsi_io { 1702 uint16_t DevHandle; /* 0x00 */ 1703 uint8_t ChainOffset; /* 0x02 */ 1704 uint8_t Function; /* 0x03 */ 1705 uint16_t Reserved1; /* 0x04 */ 1706 uint8_t Reserved2; /* 0x06 */ 1707 uint8_t MsgFlags; /* 0x07 */ 1708 uint8_t VP_ID; /* 0x08 */ 1709 uint8_t VF_ID; /* 0x09 */ 1710 uint16_t Reserved3; /* 0x0A */ 1711 uint32_t SenseBufferLowAddress; /* 0x0C */ 1712 uint16_t SGLFlags; /* 0x10 */ 1713 uint8_t SenseBufferLength; /* 0x12 */ 1714 uint8_t Reserved4; /* 0x13 */ 1715 uint8_t SGLOffset0; /* 0x14 */ 1716 uint8_t SGLOffset1; /* 0x15 */ 1717 uint8_t SGLOffset2; /* 0x16 */ 1718 uint8_t SGLOffset3; /* 0x17 */ 1719 uint32_t SkipCount; /* 0x18 */ 1720 uint32_t DataLength; /* 0x1C */ 1721 uint32_t BidirectionalDataLength; /* 0x20 */ 1722 uint16_t IoFlags; /* 0x24 */ 1723 uint16_t EEDPFlags; /* 0x26 */ 1724 uint32_t EEDPBlockSize; /* 0x28 */ 1725 uint32_t SecondaryReferenceTag; /* 0x2C */ 1726 uint16_t SecondaryApplicationTag; /* 0x30 */ 1727 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1728 uint8_t LUN[8]; /* 0x34 */ 1729 uint32_t Control; /* 0x3C */ 1730 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1731 MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1732 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1733 } __packed; 1734 1735 /* 1736 * MPT RAID MFA IO Descriptor. 1737 */ 1738 typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1739 uint32_t RequestFlags : 8; 1740 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1741 uint32_t MessageAddress2; /* bits 61:32 */ 1742 } MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1743 1744 struct mfi_mpi2_request_header { 1745 uint8_t RequestFlags; /* 0x00 */ 1746 uint8_t MSIxIndex; /* 0x01 */ 1747 uint16_t SMID; /* 0x02 */ 1748 uint16_t LMID; /* 0x04 */ 1749 }; 1750 1751 /* defines for the RequestFlags field */ 1752 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1753 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1754 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1755 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1756 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1757 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1758 1759 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1760 1761 struct mfi_mpi2_request_high_priority { 1762 struct mfi_mpi2_request_header header; 1763 uint16_t reserved; 1764 }; 1765 1766 struct mfi_mpi2_request_scsi_io { 1767 struct mfi_mpi2_request_header header; 1768 uint16_t scsi_io_dev_handle; 1769 }; 1770 1771 struct mfi_mpi2_request_scsi_target { 1772 struct mfi_mpi2_request_header header; 1773 uint16_t scsi_target_io_index; 1774 }; 1775 1776 /* Request Descriptors */ 1777 union mfi_mpi2_request_descriptor { 1778 struct mfi_mpi2_request_header header; 1779 struct mfi_mpi2_request_high_priority high_priority; 1780 struct mfi_mpi2_request_scsi_io scsi_io; 1781 struct mfi_mpi2_request_scsi_target scsi_target; 1782 uint64_t words; 1783 }; 1784 1785 1786 struct mfi_mpi2_reply_header { 1787 uint8_t ReplyFlags; /* 0x00 */ 1788 uint8_t MSIxIndex; /* 0x01 */ 1789 uint16_t SMID; /* 0x02 */ 1790 }; 1791 1792 /* defines for the ReplyFlags field */ 1793 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1794 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1795 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1796 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1797 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1798 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1799 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1800 1801 /* values for marking a reply descriptor as unused */ 1802 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1803 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1804 1805 struct mfi_mpi2_reply_default { 1806 struct mfi_mpi2_reply_header header; 1807 uint32_t DescriptorTypeDependent2; 1808 }; 1809 1810 struct mfi_mpi2_reply_address { 1811 struct mfi_mpi2_reply_header header; 1812 uint32_t ReplyFrameAddress; 1813 }; 1814 1815 struct mfi_mpi2_reply_scsi_io { 1816 struct mfi_mpi2_reply_header header; 1817 uint16_t TaskTag; /* 0x04 */ 1818 uint16_t Reserved1; /* 0x06 */ 1819 }; 1820 1821 struct mfi_mpi2_reply_target_assist { 1822 struct mfi_mpi2_reply_header header; 1823 uint8_t SequenceNumber; /* 0x04 */ 1824 uint8_t Reserved1; /* 0x04 */ 1825 uint16_t IoIndex; /* 0x06 */ 1826 }; 1827 1828 struct mfi_mpi2_reply_target_cmd_buffer { 1829 struct mfi_mpi2_reply_header header; 1830 uint8_t SequenceNumber; /* 0x04 */ 1831 uint8_t Flags; /* 0x04 */ 1832 uint16_t InitiatorDevHandle; /* 0x06 */ 1833 uint16_t IoIndex; /* 0x06 */ 1834 }; 1835 1836 struct mfi_mpi2_reply_raid_accel { 1837 struct mfi_mpi2_reply_header header; 1838 uint8_t SequenceNumber; /* 0x04 */ 1839 uint32_t Reserved; /* 0x04 */ 1840 }; 1841 1842 /* union of Reply Descriptors */ 1843 union mfi_mpi2_reply_descriptor { 1844 struct mfi_mpi2_reply_header header; 1845 struct mfi_mpi2_reply_scsi_io scsi_io; 1846 struct mfi_mpi2_reply_target_assist target_assist; 1847 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1848 struct mfi_mpi2_reply_raid_accel raid_accel; 1849 struct mfi_mpi2_reply_default reply_default; 1850 uint64_t words; 1851 }; 1852 1853 struct IO_REQUEST_INFO { 1854 uint64_t ldStartBlock; 1855 uint32_t numBlocks; 1856 uint16_t ldTgtId; 1857 uint8_t isRead; 1858 uint16_t devHandle; 1859 uint64_t pdBlock; 1860 uint8_t fpOkForIo; 1861 }; 1862 1863 #define MFI_SCSI_MAX_TARGETS 128 1864 #define MFI_SCSI_MAX_LUNS 8 1865 #define MFI_SCSI_INITIATOR_ID 255 1866 #define MFI_SCSI_MAX_CMDS 8 1867 #define MFI_SCSI_MAX_CDB_LEN 16 1868 1869 #endif /* _MFIREG_H */ 1870