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Searched refs:HSW_TVIDEO_DIP_CTL (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/i915/
HDintel_hdmi.c382 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); in hsw_write_infoframe()
415 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); in hsw_infoframe_enabled()
835 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); in hsw_set_infoframes()
HDi915_reg.h7409 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) macro