Searched refs:HDMI_ACR_44_1 (Results 1 – 9 of 9) sorted by relevance
| /dragonfly/sys/dev/drm/amd/display/dc/dce/ |
| HD | dce_stream_encoder.h | 80 SRI(HDMI_ACR_44_1, DIG, id),\
184 SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
679 uint32_t HDMI_ACR_44_1; member
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| HD | dce_stream_encoder.c | 1372 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); in dce110_se_setup_hdmi_audio()
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| /dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
| HD | dcn10_stream_encoder.h | 70 SRI(HDMI_ACR_44_1, DIG, id),\
148 uint32_t HDMI_ACR_44_1; member
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| HD | dcn10_stream_encoder.c | 1227 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); in enc1_se_setup_hdmi_audio()
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| /dragonfly/sys/dev/drm/radeon/ |
| HD | evergreen_hdmi.c | 96 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); in evergreen_hdmi_update_acr()
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| HD | rv770d.h | 793 #define HDMI_ACR_44_1 0x74b8 macro
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| HD | evergreend.h | 647 #define HDMI_ACR_44_1 0x70e8 macro
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| HD | dce_v10_0.c | 1477 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v10_0_afmt_update_ACR()
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| HD | dce_v11_0.c | 1519 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v11_0_afmt_update_ACR()
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