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Searched refs:GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_sh_mask.h4836 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL macro
HDgfx_7_2_sh_mask.h5127 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f macro
HDgfx_8_1_sh_mask.h6447 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f macro
HDgfx_8_0_sh_mask.h5913 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_sh_mask.h21147 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK … macro
HDgc_9_2_1_sh_mask.h22522 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK … macro